JP2009253283A - 取外し可能な相互接続構造体 - Google Patents
取外し可能な相互接続構造体 Download PDFInfo
- Publication number
- JP2009253283A JP2009253283A JP2009075413A JP2009075413A JP2009253283A JP 2009253283 A JP2009253283 A JP 2009253283A JP 2009075413 A JP2009075413 A JP 2009075413A JP 2009075413 A JP2009075413 A JP 2009075413A JP 2009253283 A JP2009253283 A JP 2009253283A
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- Prior art keywords
- layer
- electronic device
- base insulating
- insulating layer
- metal
- Prior art date
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- Granted
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Images
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31511—Of epoxy ether
- Y10T428/31515—As intermediate layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31652—Of asbestos
- Y10T428/31663—As siloxane, silicone or silane
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/31504—Composite [nonstructural laminate]
- Y10T428/31678—Of metal
Abstract
【効果】ベース絶縁層は第1の金属層及び取外し可能な層を介して電子デバイスに固定され、第1の金属層及び取外し可能な層は第1の金属層及び取外し可能な層がその軟化点又は融点より高い温度に暴露された場合にベース絶縁層を電子デバイスから解放することができる。
【選択図】図3
Description
12 第1の表面
14 第2の表面
16 接着剤層
18 電子デバイス
20 第1の表面
22 第2の表面
23 I/Oコンタクト
24 第1の金属層
25 第2の金属層
26 取外し可能な層
80 ベース基板
81 第1の表面
82 第2の表面
83 コンタクトパッド
86 第1の金属層
88 取外し可能な層
90 電子デバイス
92 第1の表面
93 第2の表面
94 I/Oコンタクト
96 導電性要素
98 アンダーフィル層
Claims (10)
- 第1の表面12及び第2の表面14を有するベース絶縁層10、
第1の表面20及び第2の表面22を有する電子デバイス18、
電子デバイス18の第1の表面20上に配置された1以上のI/Oコンタクト23、
電子デバイス18の第1の表面20とベース絶縁層10の第2の表面14との間に配設された接着剤層16、
I/Oコンタクト23上に配設された第1の金属層24、並びに
電子デバイス18の第1の表面20とベース絶縁層10の第2の表面14との間に配設されかつ第1の金属層24に隣接して配置された取外し可能な層26
を含んでなる電子部品であって、
ベース絶縁層10は第1の金属層24及び取外し可能な層26を介して電子デバイス18に固定され、第1の金属層24及び取外し可能な層26は第1の金属層24及び取外し可能な層26がその軟化点又は融点より高い温度に暴露された場合にベース絶縁層10を電子デバイス18から解放することができる、電子部品。 - 第1の金属層24が鉛、銀、スズ、ヒ素、白金、銅、ランタン、ナトリウム、リン又はこれらの2種以上の組合せからなる、請求項1記載の電子部品。
- 取外し可能な層26及び第1の金属層24の各々が電子デバイス18の最高損傷閾値温度より低い軟化点又は融点を有し、取外し可能な層26及び第1の金属層24をその軟化点又は融点より高いが電子デバイス18の最高損傷閾値温度より低い温度に暴露した場合に電子デバイス18をベース絶縁層10の第2の表面14から取り外すことができる、請求項1記載の電子部品。
- 取外し可能な層26及び第1の金属層24の各々が約250〜約350℃の軟化点又は融点を有する、請求項3記載の電子部品。
- 取外し可能な層26及び第1の金属層24の各々がベース絶縁層10の最高損傷閾値温度より低い軟化点又は融点を有し、取外し可能な層26及び第1の金属層24をその軟化点又は融点より高いがベース絶縁層10の最高損傷閾値温度より低い温度に暴露した場合に電子デバイス18をベース絶縁層10の第2の表面から取り外すことができる、請求項1記載の電子部品。
- さらに、第1の金属層24の表面上に配置されかつ取外し可能な層26に隣接して配置された第2の金属層25を含んでいて、ベース絶縁層10は取外し可能な層26並びに第1及び第2の金属層24、25を介して電子デバイス18に固定され、取外し可能な層26並びに第1及び/又は第2の金属層24、25は取外し可能な層26並びに第1及び/又は第2の金属層24、25がその軟化点又は融点より高い温度に暴露された場合にベース絶縁層10を電子デバイス18から解放することができる、請求項1記載の電子部品。
- 第2の金属層25が鉛、銅、銀、カドミウム、スズ、タリウム、亜鉛又はこれらの2種以上の組合せからなる、請求項6記載の電子部品。
- 取外し可能な層26、第1の金属層24及び/又は第2の金属層25が電子デバイス18の最高損傷閾値温度より低い軟化点又は融点を有し、取外し可能な層26、第1の金属層24及び第2の金属層25をその軟化点又は融点より高いが電子デバイス18の最高損傷閾値温度より低い温度に暴露した場合に電子デバイス18をベース絶縁層10の第2の表面14から取り外すことができる、請求項6記載の電子部品。
- 取外し可能な層26、第1の金属層24又は第2の金属層25がベース絶縁層10の最高損傷閾値温度より低い軟化点又は融点を有し、取外し可能な層26、第1の金属層24及び第2の金属層25をその軟化点又は融点より高いがベース絶縁層10の最高損傷閾値温度より低い温度に暴露した場合に電子デバイス18をベース絶縁層10の第2の表面14から取り外すことができる、請求項6記載の電子部品。
- 第1の表面81及び第2の表面82を有するベース基板80、
第1の表面92及び第2の表面93を有する電子デバイス90、
ベース基板80の第2の表面82上に配設された1以上のコンタクトパッド83、
コンタクトパッド83上に配設された第1の金属層86、
ベース基板80の第2の表面82と電子デバイス90の第1の表面92との間に配設されかつ第1の金属層86に隣接して配置された取外し可能な層88、
電子デバイス90の第1の表面92上に配置された1以上のI/Oコンタクト94、
1以上のI/Oコンタクト94をベース基板80上に配置された1以上のコンタクトパッド83に電気的に接続する1以上の導電性要素96、並びに
電子デバイス90の第1の表面92とベース基板80の第2の表面82との間に配設されたアンダーフィル層98
を含んでなる電子アセンブリであって、
ベース基板80は第1の金属層86及び取外し可能な層88を介して電子デバイス90に固定され、第1の金属層86及び取外し可能な層88は第1の金属層86及び取外し可能な層88がその軟化点又は融点より高い温度に暴露された場合に電子デバイス90をベース基板80から解放することができる、電子アセンブリ。
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US12/061,141 US9953910B2 (en) | 2007-06-21 | 2008-04-02 | Demountable interconnect structure |
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EP2107600A2 (en) | 2009-10-07 |
TW201001646A (en) | 2010-01-01 |
US20080318027A1 (en) | 2008-12-25 |
JP5420287B2 (ja) | 2014-02-19 |
EP2107600B1 (en) | 2016-05-11 |
KR101571898B1 (ko) | 2015-11-26 |
KR20090105858A (ko) | 2009-10-07 |
US9953910B2 (en) | 2018-04-24 |
EP2107600A3 (en) | 2012-11-28 |
TWI548045B (zh) | 2016-09-01 |
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