CA2818040C - Integrated circuit package and method of making same - Google Patents

Integrated circuit package and method of making same Download PDF

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Publication number
CA2818040C
CA2818040C CA2818040A CA2818040A CA2818040C CA 2818040 C CA2818040 C CA 2818040C CA 2818040 A CA2818040 A CA 2818040A CA 2818040 A CA2818040 A CA 2818040A CA 2818040 C CA2818040 C CA 2818040C
Authority
CA
Canada
Prior art keywords
adhesive
die
layer
adhesive layer
chip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2818040A
Other languages
English (en)
French (fr)
Other versions
CA2818040A1 (en
Inventor
Paul Alan Mcconnelee
Arun Virupaksha Gowda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CA2818040A1 publication Critical patent/CA2818040A1/en
Application granted granted Critical
Publication of CA2818040C publication Critical patent/CA2818040C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10W90/00—
    • H10W42/00—
    • H10P72/7402—
    • H10W70/05—
    • H10W70/09—
    • H10W70/095—
    • H10W70/60—
    • H10W70/611—
    • H10W70/635—
    • H10W70/65—
    • H10W70/685—
    • H10W72/30—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H10P72/7416—
    • H10P72/7422—
    • H10P72/744—
    • H10W70/093—
    • H10W72/01304—
    • H10W72/01323—
    • H10W72/01333—
    • H10W72/01336—
    • H10W72/01365—
    • H10W72/01371—
    • H10W72/0198—
    • H10W72/073—
    • H10W72/07338—
    • H10W72/354—
    • H10W72/9413—
    • H10W90/734—
    • H10W99/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
CA2818040A 2012-06-15 2013-06-06 Integrated circuit package and method of making same Active CA2818040C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/524,369 2012-06-15
US13/524,369 US9117813B2 (en) 2012-06-15 2012-06-15 Integrated circuit package and method of making same

Publications (2)

Publication Number Publication Date
CA2818040A1 CA2818040A1 (en) 2013-12-15
CA2818040C true CA2818040C (en) 2020-09-22

Family

ID=48578955

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2818040A Active CA2818040C (en) 2012-06-15 2013-06-06 Integrated circuit package and method of making same

Country Status (6)

Country Link
US (2) US9117813B2 (enExample)
EP (1) EP2674970A3 (enExample)
JP (1) JP2014003292A (enExample)
KR (1) KR102027339B1 (enExample)
CA (1) CA2818040C (enExample)
TW (1) TWI578452B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11128786B2 (en) * 2014-11-21 2021-09-21 Apple Inc. Bending a circuit-bearing die
US9666516B2 (en) 2014-12-01 2017-05-30 General Electric Company Electronic packages and methods of making and using the same
US20170064821A1 (en) * 2015-08-31 2017-03-02 Kristof Darmawikarta Electronic package and method forming an electrical package
JP2017073472A (ja) * 2015-10-07 2017-04-13 株式会社ディスコ 半導体装置の製造方法
KR102294537B1 (ko) 2016-03-12 2021-08-27 닝보 써니 오포테크 코., 엘티디. 카메라 모듈, 그 감광성 부품 및 그 제조 방법
KR102555721B1 (ko) 2018-08-20 2023-07-17 삼성전자주식회사 플립 칩 본딩 방법
CN120229024B (zh) * 2025-05-29 2025-08-29 浙江鼎晶科技有限公司 一种Micro OLED的喷墨方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4793883A (en) 1986-07-14 1988-12-27 National Starch And Chemical Corporation Method of bonding a semiconductor chip to a substrate
US5353195A (en) 1993-07-09 1994-10-04 General Electric Company Integral power and ground structure for multi-chip modules
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5776799A (en) * 1996-11-08 1998-07-07 Samsung Electronics Co., Ltd. Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6773962B2 (en) 2001-03-15 2004-08-10 General Electric Company Microelectromechanical system device packaging method
KR100517075B1 (ko) 2003-08-11 2005-09-26 삼성전자주식회사 반도체 소자 제조 방법
US7243421B2 (en) * 2003-10-29 2007-07-17 Conductive Inkjet Technology Limited Electrical connection of components
US7101620B1 (en) * 2004-09-07 2006-09-05 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
US8049338B2 (en) 2006-04-07 2011-11-01 General Electric Company Power semiconductor module and fabrication method
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
KR100999919B1 (ko) * 2008-09-08 2010-12-13 삼성전기주식회사 인쇄회로기판 제조 방법
EP2184774A1 (en) 2008-11-05 2010-05-12 General Electric Company Low-temperature recoverable electronic component
US7851266B2 (en) * 2008-11-26 2010-12-14 Micron Technologies, Inc. Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on microelectronic device wafers, and methods of molding adhesives on microelectronic device wafers
US8008125B2 (en) 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
JP2011253939A (ja) * 2010-06-02 2011-12-15 Sony Chemical & Information Device Corp ウエハのダイシング方法、接続方法及び接続構造体
US8623699B2 (en) 2010-07-26 2014-01-07 General Electric Company Method of chip package build-up
US8114712B1 (en) 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package

Also Published As

Publication number Publication date
KR20130141387A (ko) 2013-12-26
TWI578452B (zh) 2017-04-11
CA2818040A1 (en) 2013-12-15
EP2674970A2 (en) 2013-12-18
US20150287699A1 (en) 2015-10-08
US20130334706A1 (en) 2013-12-19
TW201405724A (zh) 2014-02-01
US9117813B2 (en) 2015-08-25
KR102027339B1 (ko) 2019-10-01
JP2014003292A (ja) 2014-01-09
US9613932B2 (en) 2017-04-04
EP2674970A3 (en) 2014-03-26

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Effective date: 20180328