JP2013535820A - 狭い銅充填ビアの導電率を向上させるための方法及び構造体 - Google Patents
狭い銅充填ビアの導電率を向上させるための方法及び構造体 Download PDFInfo
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Abstract
【解決手段】 一態様において、Cu充填ビアを製造する方法が提供される。方法は、以下のステップを含む。誘電体内にビアをエッチングする。ビアを拡散バリアでライニングする。拡散バリアの上に、薄いルテニウム(Ru)層を共形に堆積させる。Ru層上に、薄いシードCu層を堆積させる。第1のアニールを行って、シードCu層の粒径を増大させる。ビアを付加的なCuで充填する。第2のアニールを行って、付加的なCuの粒径を増大させる。
【選択図】 図5
Description
101:ビア
120:誘電体
202:拡散バリア
202a:窒化タンタル(TaN)層
202b:タンタル(Ta)層
302:Ru層
402:シードCu層
502、602:Cu
g:粒径
w:幅
Claims (26)
- 銅充填ビアを製造するための方法であって、
誘電体内にビアをエッチングするステップと、
前記ビアを拡散バリアでライニングするステップと、
前記拡散バリアの上に、ルテニウム層を共形に堆積させるステップと、
前記ルテニウム層上に、シード銅層を堆積させるステップと、
第1のアニールを行って、前記シード銅層の粒径を増大させるステップと、
前記ビアを付加的な銅で充填するステップと、
第2のアニールを行って、前記付加的な銅の粒径を増大させるステップと、
を含む方法。 - 前記ビアを前記拡散バリアでライニングするステップは、
前記ビアをライニングするために、前記誘電体の上に窒化タンタル層を堆積させるステップと、
前記窒化タンタル層上にタンタル層を堆積させるステップと、
を含む、請求項1に記載の方法。 - 前記窒化タンタル層は、5ナノメートルから15ナノメートルまでの厚さに堆積される、請求項2に記載の方法。
- 前記窒化タンタル層は、8ナノメートルから12ナノメートルまでの厚さに堆積される、請求項2又は請求項3のいずれかに記載の方法。
- 前記タンタル層は、5ナノメートルから15ナノメートルまでの厚さに堆積される、請求項2から請求項4までのいずれかに記載の方法。
- 前記タンタル層は、8ナノメートルから12ナノメートルまでの厚さに堆積される、請求項2から請求項5までのいずれかに記載の方法。
- 前記ルテニウム層は、1ナノメートルから10ナノメートルまでの厚さに堆積される、前記請求項のいずれかに記載の方法。
- 前記ルテニウム層は、2ナノメートルから5ナノメートルまでの厚さに堆積される、前記請求項のいずれかに記載の方法。
- 前記ルテニウム層は、化学気相堆積を用いて前記拡散バリアの上に堆積される、前記請求項のいずれかに記載の方法。
- ルテニウムカルボニルが、前記化学気相堆積のための前駆体として用いられる、請求項9に記載の方法。
- 前記ルテニウム層は、原子層堆積を用いて前記拡散バリアの上に堆積される、請求項1から請求項8までのいずれかに記載の方法。
- ルテニウムカルボニルが、前記原子層堆積のための前駆体として用いられる、請求項11に記載の方法。
- 前記ルテニウム層は、スパッタ堆積プロセスを用いて前記拡散バリアの上に堆積される、請求項1から請求項8までのいずれかに記載の方法。
- 前記シード銅層は、20ナノメートルから100ナノメートルまでの厚さに堆積される、前記請求項のいずれかに記載の方法。
- 前記シード銅層は、25ナノメートルから35ナノメートルまでの厚さに堆積される、前記請求項のいずれかに記載の方法。
- 前記シード銅層は、スパッタ堆積プロセスを用いて堆積される、前記請求項のいずれかに記載の方法。
- 前記第1のアニールは、フォーミング・ガス中で、150℃から350℃までの温度で行われる、前記請求項のいずれかに記載の方法。
- 付加的な銅を前記ビア内にめっきするステップをさらに含む、前記請求項のいずれかに記載の方法。
- 前記付加的な銅を前記ビア内に電気めっきする、請求項18に記載の方法。
- 前記第2のアニールは、フォーミング・ガス中で、150℃から350℃までの温度で行われる、前記請求項のいずれかに記載の方法。
- 前記ビアを付加的な銅で充填するステップは、前記第1のアニールを行うステップに応じたものである、前記請求項のいずれかに記載の方法。
- 誘電体内に形成された銅充填ビアであって、
ビアと、
前記ビアをライニングする拡散バリアと、
前記拡散バリア上に共形に堆積されたルテニウム層と、
前記ルテニウム層上に堆積されたシード銅層と、
前記銅充填ビアを形成するために前記ビアを充填する、前記シード銅層上にめっきされた付加的な銅と、
を含み、前記付加的な銅は、前記ビアの幅の少なくとも0.5倍の平均粒子幅を有する、銅充填ビア。 - 前記ビアは、20ナノメートルから50ナノメートルまでの幅を有する、請求項22に記載の銅充填ビア。
- 前記拡散バリアは、
前記ビアをライニングする窒化タンタル層と、
前記窒化タンタル層上のタンタル層と
を含む、請求項22又は請求項23のいずれかに記載の銅充填ビア。 - 前記ルテニウム層は、1ナノメートルから10ナノメートルまでの厚さを有する、請求項22から請求項24までのいずれかに記載の銅充填ビア。
- 前記シード銅層は、20ナノメートルから100ナノメートルまでの厚さを有する、請求項22から請求項25までのいずれかに記載の銅充填ビア。
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Application Number | Priority Date | Filing Date | Title |
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US12/838,597 | 2010-07-19 | ||
US12/838,597 US8661664B2 (en) | 2010-07-19 | 2010-07-19 | Techniques for forming narrow copper filled vias having improved conductivity |
PCT/EP2011/061959 WO2012010479A1 (en) | 2010-07-19 | 2011-07-13 | Method and structure to improve the conductivity of narrow copper filled vias |
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JP2013535820A true JP2013535820A (ja) | 2013-09-12 |
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US (2) | US8661664B2 (ja) |
JP (1) | JP2013535820A (ja) |
CN (1) | CN103003939A (ja) |
DE (1) | DE112011101750T5 (ja) |
GB (1) | GB2495451B (ja) |
TW (1) | TWI513378B (ja) |
WO (1) | WO2012010479A1 (ja) |
Cited By (2)
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JP2016540368A (ja) * | 2013-09-27 | 2016-12-22 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | シームレスのコバルト間隙充填を可能にする方法 |
JP2017527117A (ja) * | 2014-08-27 | 2017-09-14 | ウルトラテック インク | 改良型貫通シリコンビア |
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US9558997B2 (en) * | 2012-12-28 | 2017-01-31 | Globalfoundries Inc. | Integration of Ru wet etch and CMP for beol interconnects with Ru layer |
CN104465507A (zh) * | 2014-12-26 | 2015-03-25 | 上海集成电路研发中心有限公司 | 一种铜互连的形成方法 |
CN106158733A (zh) * | 2015-04-22 | 2016-11-23 | 中国科学院微电子研究所 | 一种铜互连结构及其制造方法 |
US10396012B2 (en) * | 2016-05-27 | 2019-08-27 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
US10312181B2 (en) | 2016-05-27 | 2019-06-04 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
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- 2011-07-13 DE DE112011101750T patent/DE112011101750T5/de not_active Ceased
- 2011-07-13 GB GB1301210.9A patent/GB2495451B/en not_active Expired - Fee Related
- 2011-07-13 WO PCT/EP2011/061959 patent/WO2012010479A1/en active Application Filing
- 2011-07-13 CN CN2011800353154A patent/CN103003939A/zh active Pending
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WO2011041522A2 (en) * | 2009-09-30 | 2011-04-07 | Tokyo Electron Limited | Methods for multi-step copper plating on a continuous ruthenium film in recessed features |
JP2013507008A (ja) * | 2009-09-30 | 2013-02-28 | 東京エレクトロン株式会社 | 切欠構造のなかで長尺状ルテニウム膜上に多段階式銅鍍金を行う方法。 |
Cited By (3)
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JP2016540368A (ja) * | 2013-09-27 | 2016-12-22 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | シームレスのコバルト間隙充填を可能にする方法 |
US10699946B2 (en) | 2013-09-27 | 2020-06-30 | Applied Materials, Inc. | Method of enabling seamless cobalt gap-fill |
JP2017527117A (ja) * | 2014-08-27 | 2017-09-14 | ウルトラテック インク | 改良型貫通シリコンビア |
Also Published As
Publication number | Publication date |
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CN103003939A (zh) | 2013-03-27 |
WO2012010479A1 (en) | 2012-01-26 |
TWI513378B (zh) | 2015-12-11 |
GB2495451B (en) | 2016-03-02 |
GB2495451A (en) | 2013-04-10 |
TW201223358A (en) | 2012-06-01 |
US20120012372A1 (en) | 2012-01-19 |
DE112011101750T5 (de) | 2013-07-18 |
US20140151097A1 (en) | 2014-06-05 |
US8661664B2 (en) | 2014-03-04 |
US9392690B2 (en) | 2016-07-12 |
GB201301210D0 (en) | 2013-03-06 |
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