JP4536809B2 - 銅めっきされた高アスペクト比のビア、及びその製造する方法 - Google Patents
銅めっきされた高アスペクト比のビア、及びその製造する方法 Download PDFInfo
- Publication number
- JP4536809B2 JP4536809B2 JP2008268013A JP2008268013A JP4536809B2 JP 4536809 B2 JP4536809 B2 JP 4536809B2 JP 2008268013 A JP2008268013 A JP 2008268013A JP 2008268013 A JP2008268013 A JP 2008268013A JP 4536809 B2 JP4536809 B2 JP 4536809B2
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- Prior art keywords
- layer
- copper
- diffusion barrier
- thickness
- deposited
- Prior art date
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- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Other Surface Treatments For Metallic Materials (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
101:ビア
120、220:誘電体層
130、230:拡散バリア層
140:シード層
201:高アスペクト比ビア
240:銅シード層
250:ルテニウムシード層
260:銅(Cu)
Claims (7)
- 銅めっきされたビアを製造する方法であって、
誘電体層内に5:1以上の深さ対幅のアスペクト比を有するビアをエッチングするステップと、
前記ビア内及び前記誘電体層の1つ又は複数の表面の上に拡散バリア層を堆積させるステップと、
前記拡散バリア層の上に前記ビアの側壁上を連続的に被覆する厚さを有しないようにして、1ナノメートルから5ナノメートルまでの厚さを有する銅層を堆積させるステップと、
前記銅層の上に5ナノメートル以下の厚さを有するルテニウム層を堆積させるステップであって、ルテニウムカルボニル前駆体から化学気相堆積を用いてルテニウム層を前記ビアの側壁上の連続的な被覆を確実にする厚さであってCu研磨スラリーで化学機械研磨可能な厚さに堆積させるステップと、
前記ルテニウム層の上に銅を均一に電気めっきして前記ビアを銅で充填するステップと
を含む方法。 - 前記銅層は、前記ビアの張出し及び閉鎖を回避するために、めっき中に通電層として働くのに必要な厚さにまでしか堆積されない、請求項1に記載の方法。
- 化学気相堆積、原子層堆積、蒸着、スパッタリング、溶液ベースの技術、又はスピンオン・コーティングを用いて、基板の上に前記誘電体層を堆積させるステップをさらに含む、請求項1に記載の方法。
- 前記ビアは、反応性イオンエッチングを用いて前記誘電体内にエッチングされる、請求項1に記載の方法。
- 前記拡散バリア層は、化学気相堆積、原子層堆積、又はスパッタリングを用いて堆積される、請求項1に記載の方法。
- 前記銅層は、化学気相堆積、原子層堆積、又はスパッタリングを用いて堆積される、請求項1に記載の方法。
- 前記電気めっきされた銅、前記ルテニウム層、前記銅層及び前記拡散バリア層を前記誘電体層の上面まで平削りするステップをさらに含む、請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/163,172 US7964497B2 (en) | 2008-06-27 | 2008-06-27 | Structure to facilitate plating into high aspect ratio vias |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010010642A JP2010010642A (ja) | 2010-01-14 |
JP4536809B2 true JP4536809B2 (ja) | 2010-09-01 |
Family
ID=40635481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008268013A Expired - Fee Related JP4536809B2 (ja) | 2008-06-27 | 2008-10-16 | 銅めっきされた高アスペクト比のビア、及びその製造する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7964497B2 (ja) |
EP (1) | EP2139034A1 (ja) |
JP (1) | JP4536809B2 (ja) |
CN (1) | CN101615591A (ja) |
TW (1) | TW201017821A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8661664B2 (en) | 2010-07-19 | 2014-03-04 | International Business Machines Corporation | Techniques for forming narrow copper filled vias having improved conductivity |
US9748173B1 (en) * | 2016-07-06 | 2017-08-29 | International Business Machines Corporation | Hybrid interconnects and method of forming the same |
US10847463B2 (en) * | 2017-08-22 | 2020-11-24 | Applied Materials, Inc. | Seed layers for copper interconnects |
US11527476B2 (en) * | 2020-09-11 | 2022-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure of semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002075994A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6790773B1 (en) * | 2002-08-28 | 2004-09-14 | Novellus Systems, Inc. | Process for forming barrier/seed structures for integrated circuits |
US20050095846A1 (en) * | 2003-10-31 | 2005-05-05 | Basol Bulent M. | System and method for defect free conductor deposition on substrates |
US20060199372A1 (en) * | 2005-03-01 | 2006-09-07 | Applied Materials, Inc. | Reduction of copper dewetting by transition metal deposition |
JP2008041700A (ja) * | 2006-08-01 | 2008-02-21 | Tokyo Electron Ltd | 成膜方法、成膜装置及び記憶媒体 |
Family Cites Families (17)
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KR100249828B1 (ko) * | 1997-09-18 | 2000-04-01 | 정선종 | 확산방지막 형성방법 |
KR100404649B1 (ko) * | 1998-02-23 | 2003-11-10 | 가부시끼가이샤 히다치 세이사꾸쇼 | 반도체장치 및 그 제조방법 |
JP4342075B2 (ja) * | 2000-03-28 | 2009-10-14 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7010056B1 (en) * | 2000-10-10 | 2006-03-07 | Freescale Semiconductor, Inc. | System and method for generating ultra wideband pulses |
US6403491B1 (en) * | 2000-11-01 | 2002-06-11 | Applied Materials, Inc. | Etch method using a dielectric etch chamber with expanded process window |
JP4028393B2 (ja) * | 2003-01-09 | 2007-12-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
US6974768B1 (en) * | 2003-01-15 | 2005-12-13 | Novellus Systems, Inc. | Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films |
US7060619B2 (en) * | 2003-03-04 | 2006-06-13 | Infineon Technologies Ag | Reduction of the shear stress in copper via's in organic interlayer dielectric material |
US7211508B2 (en) * | 2003-06-18 | 2007-05-01 | Applied Materials, Inc. | Atomic layer deposition of tantalum based barrier materials |
US7476618B2 (en) * | 2004-10-26 | 2009-01-13 | Asm Japan K.K. | Selective formation of metal layers in an integrated circuit |
US7279421B2 (en) | 2004-11-23 | 2007-10-09 | Tokyo Electron Limited | Method and deposition system for increasing deposition rates of metal layers from metal-carbonyl precursors |
US8435351B2 (en) | 2004-11-29 | 2013-05-07 | Tokyo Electron Limited | Method and system for measuring a flow rate in a solid precursor delivery system |
US7396766B2 (en) | 2005-03-31 | 2008-07-08 | Tokyo Electron Limited | Low-temperature chemical vapor deposition of low-resistivity ruthenium layers |
FR2890984B1 (fr) * | 2005-09-20 | 2009-03-27 | Alchimer Sa | Procede d'electrodeposition destine au revetement d'une surface d'un substrat par un metal. |
US8222746B2 (en) * | 2006-03-03 | 2012-07-17 | Intel Corporation | Noble metal barrier layers |
US7432195B2 (en) * | 2006-03-29 | 2008-10-07 | Tokyo Electron Limited | Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features |
US8258057B2 (en) * | 2006-03-30 | 2012-09-04 | Intel Corporation | Copper-filled trench contact for transistor performance improvement |
-
2008
- 2008-06-27 US US12/163,172 patent/US7964497B2/en not_active Expired - Fee Related
- 2008-10-14 EP EP08166587A patent/EP2139034A1/en not_active Withdrawn
- 2008-10-16 JP JP2008268013A patent/JP4536809B2/ja not_active Expired - Fee Related
-
2009
- 2009-06-23 CN CN200910150840A patent/CN101615591A/zh active Pending
- 2009-06-24 TW TW098121240A patent/TW201017821A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002075994A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6790773B1 (en) * | 2002-08-28 | 2004-09-14 | Novellus Systems, Inc. | Process for forming barrier/seed structures for integrated circuits |
US20050095846A1 (en) * | 2003-10-31 | 2005-05-05 | Basol Bulent M. | System and method for defect free conductor deposition on substrates |
US20060199372A1 (en) * | 2005-03-01 | 2006-09-07 | Applied Materials, Inc. | Reduction of copper dewetting by transition metal deposition |
JP2008041700A (ja) * | 2006-08-01 | 2008-02-21 | Tokyo Electron Ltd | 成膜方法、成膜装置及び記憶媒体 |
Also Published As
Publication number | Publication date |
---|---|
TW201017821A (en) | 2010-05-01 |
CN101615591A (zh) | 2009-12-30 |
US7964497B2 (en) | 2011-06-21 |
US20090321933A1 (en) | 2009-12-31 |
JP2010010642A (ja) | 2010-01-14 |
EP2139034A1 (en) | 2009-12-30 |
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