JP2013131262A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2013131262A JP2013131262A JP2011278558A JP2011278558A JP2013131262A JP 2013131262 A JP2013131262 A JP 2013131262A JP 2011278558 A JP2011278558 A JP 2011278558A JP 2011278558 A JP2011278558 A JP 2011278558A JP 2013131262 A JP2013131262 A JP 2013131262A
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- local
- switch
- memory cell
- local bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 230000015654 memory Effects 0.000 claims abstract description 110
- 238000010586 diagram Methods 0.000 description 15
- 230000003321 amplification Effects 0.000 description 12
- 238000003199 nucleic acid amplification method Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 101100203174 Zea mays SGS3 gene Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011278558A JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
| US13/714,015 US9177619B2 (en) | 2011-12-20 | 2012-12-13 | Semiconductor device having hierarchical bit line structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011278558A JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013131262A true JP2013131262A (ja) | 2013-07-04 |
| JP2013131262A5 JP2013131262A5 (enExample) | 2014-12-18 |
Family
ID=48610003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011278558A Abandoned JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9177619B2 (enExample) |
| JP (1) | JP2013131262A (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102193885B1 (ko) | 2014-01-17 | 2020-12-22 | 삼성전자주식회사 | 감지 증폭기 및 이를 포함하는 메모리 장치 |
| ITUA20161478A1 (it) | 2016-03-09 | 2017-09-09 | St Microelectronics Srl | Circuito e metodo di lettura di una cella di memoria di un dispositivo di memoria non volatile |
| US9928888B1 (en) * | 2016-09-23 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company Limited | Low power consumption memory device |
| WO2018125135A1 (en) * | 2016-12-29 | 2018-07-05 | Intel Corporation | Sram with hierarchical bit lines in monolithic 3d integrated chips |
| US10062429B1 (en) | 2017-04-17 | 2018-08-28 | Intel Corporation | System, apparatus and method for segmenting a memory array |
| KR102381341B1 (ko) | 2017-12-18 | 2022-03-31 | 삼성전자주식회사 | 반도체 메모리 장치에서의 비트라인 센스 앰프의 레이아웃 구조 |
| US10783938B2 (en) * | 2018-06-29 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM with local bit line, input/output circuit, and global bit line |
| US10885970B2 (en) * | 2018-08-30 | 2021-01-05 | Micron Technology, Inc. | Non-linear activation for sensing circuitry |
| JP2020145344A (ja) * | 2019-03-07 | 2020-09-10 | キオクシア株式会社 | 半導体記憶装置 |
| US12094520B2 (en) * | 2021-12-29 | 2024-09-17 | Micron Technology, Inc. | Memory device layout with intersecting region between sub-wordline and sense amplifier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009024A (en) * | 1997-03-27 | 1999-12-28 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory |
| US6256221B1 (en) * | 1998-01-30 | 2001-07-03 | Silicon Aquarius, Inc. | Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
| JP5019579B2 (ja) * | 2007-01-18 | 2012-09-05 | 株式会社東芝 | 半導体記憶装置 |
| JP5680819B2 (ja) | 2008-08-29 | 2015-03-04 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | センスアンプ回路及び半導体記憶装置 |
| JP2011034614A (ja) | 2009-07-30 | 2011-02-17 | Elpida Memory Inc | 半導体装置及びこれを備えるシステム |
-
2011
- 2011-12-20 JP JP2011278558A patent/JP2013131262A/ja not_active Abandoned
-
2012
- 2012-12-13 US US13/714,015 patent/US9177619B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US9177619B2 (en) | 2015-11-03 |
| US20130155798A1 (en) | 2013-06-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130730 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141030 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20141030 |
|
| A762 | Written abandonment of application |
Free format text: JAPANESE INTERMEDIATE CODE: A762 Effective date: 20141222 |