JP2013131262A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2013131262A5 JP2013131262A5 JP2011278558A JP2011278558A JP2013131262A5 JP 2013131262 A5 JP2013131262 A5 JP 2013131262A5 JP 2011278558 A JP2011278558 A JP 2011278558A JP 2011278558 A JP2011278558 A JP 2011278558A JP 2013131262 A5 JP2013131262 A5 JP 2013131262A5
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- transistor
- local bit
- local
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011278558A JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
| US13/714,015 US9177619B2 (en) | 2011-12-20 | 2012-12-13 | Semiconductor device having hierarchical bit line structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011278558A JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013131262A JP2013131262A (ja) | 2013-07-04 |
| JP2013131262A5 true JP2013131262A5 (enExample) | 2014-12-18 |
Family
ID=48610003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011278558A Abandoned JP2013131262A (ja) | 2011-12-20 | 2011-12-20 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9177619B2 (enExample) |
| JP (1) | JP2013131262A (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102193885B1 (ko) | 2014-01-17 | 2020-12-22 | 삼성전자주식회사 | 감지 증폭기 및 이를 포함하는 메모리 장치 |
| ITUA20161478A1 (it) * | 2016-03-09 | 2017-09-09 | St Microelectronics Srl | Circuito e metodo di lettura di una cella di memoria di un dispositivo di memoria non volatile |
| US9928888B1 (en) * | 2016-09-23 | 2018-03-27 | Taiwan Semiconductor Manufacturing Company Limited | Low power consumption memory device |
| US11114446B2 (en) * | 2016-12-29 | 2021-09-07 | Intel Corporation | SRAM with hierarchical bit lines in monolithic 3D integrated chips |
| US10062429B1 (en) | 2017-04-17 | 2018-08-28 | Intel Corporation | System, apparatus and method for segmenting a memory array |
| KR102381341B1 (ko) | 2017-12-18 | 2022-03-31 | 삼성전자주식회사 | 반도체 메모리 장치에서의 비트라인 센스 앰프의 레이아웃 구조 |
| US10783938B2 (en) * | 2018-06-29 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM with local bit line, input/output circuit, and global bit line |
| US10885970B2 (en) * | 2018-08-30 | 2021-01-05 | Micron Technology, Inc. | Non-linear activation for sensing circuitry |
| JP2020145344A (ja) * | 2019-03-07 | 2020-09-10 | キオクシア株式会社 | 半導体記憶装置 |
| US12094520B2 (en) * | 2021-12-29 | 2024-09-17 | Micron Technology, Inc. | Memory device layout with intersecting region between sub-wordline and sense amplifier |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009024A (en) * | 1997-03-27 | 1999-12-28 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory |
| US6256221B1 (en) * | 1998-01-30 | 2001-07-03 | Silicon Aquarius, Inc. | Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines |
| JP5019579B2 (ja) * | 2007-01-18 | 2012-09-05 | 株式会社東芝 | 半導体記憶装置 |
| JP5680819B2 (ja) | 2008-08-29 | 2015-03-04 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | センスアンプ回路及び半導体記憶装置 |
| JP2011034614A (ja) | 2009-07-30 | 2011-02-17 | Elpida Memory Inc | 半導体装置及びこれを備えるシステム |
-
2011
- 2011-12-20 JP JP2011278558A patent/JP2013131262A/ja not_active Abandoned
-
2012
- 2012-12-13 US US13/714,015 patent/US9177619B2/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2013131262A5 (enExample) | ||
| CN101556828B (zh) | 非易失性存储设备单位单元和具有它的非易失性存储设备 | |
| JP2014010885A5 (enExample) | ||
| JP2014142989A5 (enExample) | ||
| TWI456572B (zh) | 半導體記憶裝置 | |
| TW200701228A (en) | Voltage supply circuit and semiconductor memory | |
| JP2013157044A5 (enExample) | ||
| JP2016157504A5 (enExample) | ||
| US9990962B2 (en) | Data sense amplifier and a memory device with open or folded bit line structure | |
| US8929129B2 (en) | Semiconductor device | |
| TWI527056B (zh) | Low power memory | |
| US9934828B2 (en) | Shared sense amplifier and write driver | |
| JP2010524304A5 (enExample) | ||
| TW201447906A (zh) | 半導體記憶體 | |
| JP2015041388A5 (enExample) | ||
| US8115550B2 (en) | Transmitter | |
| US8730749B2 (en) | Data transmission circuit and semiconductor apparatus using the same | |
| JP2011035597A5 (enExample) | ||
| JP2007504592A5 (enExample) | ||
| US8284598B2 (en) | Semiconductor memory device | |
| US9030890B2 (en) | Semiconductor memory apparatus | |
| JP2006221796A5 (enExample) | ||
| JP2014142994A5 (enExample) | ||
| JP4872976B2 (ja) | 強誘電体メモリ装置 | |
| KR100744028B1 (ko) | 차동증폭장치 |