JP2013115145A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP2013115145A JP2013115145A JP2011258116A JP2011258116A JP2013115145A JP 2013115145 A JP2013115145 A JP 2013115145A JP 2011258116 A JP2011258116 A JP 2011258116A JP 2011258116 A JP2011258116 A JP 2011258116A JP 2013115145 A JP2013115145 A JP 2013115145A
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- JP
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- Prior art keywords
- semiconductor element
- resist layer
- solder
- solder resist
- mounting portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
【解決手段】絶縁基板に半導体素子接続パッド及びソルダーレジスト層5bを形成する工程と、前記半導体素子接続パッド上にソルダーレジスト層5bの上面より高い半田バンプB1を溶着する工程と、ソルダーレジスト層5b及び半田バンプB1上にソルダーレジスト層5bを弾性変形で凹ませつつ半田バンプB1を塑性変形で押潰す様に押圧ローラーRを転動させて半田バンプB1の頭頂部をソルダーレジスト層5bの上面より低い位置となるように平坦化する工程とを行なう。
【選択図】図3
Description
6 半導体素子接続パッド
10 配線基板
10a 半導体素子搭載部
B1 半田バンプ
E 半導体素子
R 押圧ローラー
S 絶縁基板
Claims (1)
- 上面中央部に半導体素子が搭載される半導体素子搭載部を有する絶縁基板と、前記半導体素子搭載部に配設された複数の半導体素子接続パッドと、前記絶縁基板の上面に前記半導体素子搭載部を囲繞するようにして被着されており、前記半導体素子接続パッドの上面より高い上面を有するソルダーレジスト層と、前記半導体素子接続パッド上に溶着されており、頭頂部が平坦化された半田バンプとを備える配線基板の製造方法であって、前記絶縁基板の上面に前記半導体素子接続パッドおよび前記ソルダーレジスト層を形成する工程と、前記半導体素子接続パッド上に前記ソルダーレジスト層の上面よりも突出する高さの半田バンプを溶着する工程と、前記ソルダーレジスト層上および前記半田バンプ上に、前記ソルダーレジスト層を弾性変形で凹ませつつ前記半田バンプの頭頂部を塑性変形で押し潰すように押圧ローラーを転動させることにより前記頭頂部を前記ソルダーレジスト層の上面より低い位置となるようなに平坦化する工程とを行なうことを特徴とする配線基板の製造方法。
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JP2011258116A JP5992676B2 (ja) | 2011-11-25 | 2011-11-25 | 配線基板の製造方法 |
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JP2011258116A JP5992676B2 (ja) | 2011-11-25 | 2011-11-25 | 配線基板の製造方法 |
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JP2013115145A true JP2013115145A (ja) | 2013-06-10 |
JP5992676B2 JP5992676B2 (ja) | 2016-09-14 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013232617A (ja) * | 2012-04-04 | 2013-11-14 | Sanei Kagaku Kk | はんだ実装基板及びその製造方法、並びに半導体装置 |
JP2015133388A (ja) * | 2014-01-10 | 2015-07-23 | 新光電気工業株式会社 | 半導体装置、半導体装置の製造方法 |
JP2019087723A (ja) * | 2017-11-08 | 2019-06-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板及びこれを含む電子素子パッケージ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004349602A (ja) * | 2003-05-26 | 2004-12-09 | Toppan Printing Co Ltd | バンプのフラッタニング用治具およびフラッタニング方法、並びに多層基板の製造方法 |
JP2007059588A (ja) * | 2005-08-24 | 2007-03-08 | Kyocer Slc Technologies Corp | 配線基板の製造方法および配線基板 |
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2011
- 2011-11-25 JP JP2011258116A patent/JP5992676B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004349602A (ja) * | 2003-05-26 | 2004-12-09 | Toppan Printing Co Ltd | バンプのフラッタニング用治具およびフラッタニング方法、並びに多層基板の製造方法 |
JP2007059588A (ja) * | 2005-08-24 | 2007-03-08 | Kyocer Slc Technologies Corp | 配線基板の製造方法および配線基板 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013232617A (ja) * | 2012-04-04 | 2013-11-14 | Sanei Kagaku Kk | はんだ実装基板及びその製造方法、並びに半導体装置 |
US9565754B2 (en) | 2012-04-04 | 2017-02-07 | San-Ei Kagaku Co., Ltd. | Solder-mounted board, production method therefor, and semiconductor device |
JP2015133388A (ja) * | 2014-01-10 | 2015-07-23 | 新光電気工業株式会社 | 半導体装置、半導体装置の製造方法 |
JP2019087723A (ja) * | 2017-11-08 | 2019-06-06 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板及びこれを含む電子素子パッケージ |
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