JP2012227779A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2012227779A JP2012227779A JP2011094264A JP2011094264A JP2012227779A JP 2012227779 A JP2012227779 A JP 2012227779A JP 2011094264 A JP2011094264 A JP 2011094264A JP 2011094264 A JP2011094264 A JP 2011094264A JP 2012227779 A JP2012227779 A JP 2012227779A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay
- clock signal
- signal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000000034 method Methods 0.000 claims description 9
- 230000001934 delay Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 14
- 238000012546 transfer Methods 0.000 description 13
- 230000001360 synchronised effect Effects 0.000 description 8
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 4
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 4
- 239000000872 buffer Substances 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 3
- 101150110298 INV1 gene Proteins 0.000 description 3
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
Landscapes
- Pulse Circuits (AREA)
- Dram (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
【解決手段】第1のクロック信号(図2のCLKIN)を遅延させて第2のクロック信号(図2のLCLK)を生成する遅延部(図2の33、34が相当する)と、第1のクロック信号と、第2のクロック信号をさらに遅延した信号(図2のRCLK)との位相を比較する位相比較回路(図2の36)と、遅延部の遅延量を決定するカウント値を遅延部に出力すると共に、位相比較回路の位相比較結果に応じてアップダウンするカウンタ回路(図2の37)と、初期設定動作時において、第1のクロック信号の周期を検知し、検知した周期に応じたカウント値の初期値をカウンタ回路に対して出力する初期遅延量制御回路(図2の30)と、を備える。
【選択図】図2
Description
12 アドレスラッチ回路
13 コマンド入力回路
14 コマンドデコード回路
15 モードレジスタ
16 リフレッシュ制御回路
17 カラムデコーダ
18 ロウデコーダ
19 メモリセルアレイ
20 クロック入力回路
21 タイミングジェネレータ
22 DLL回路
23 FIFO回路
24 入出力回路
25 内部電源発生回路
30 初期遅延量制御回路
31、31a 第1制御部
32、32a 第2制御部
33、33a、33b、DL11、DL12、DL13、DL21〜DL2m、DL31〜DL3m 遅延回路
34 遅延選択回路
35 レプリカ回路
36 位相比較回路
37 カウンタ回路
40、40a コード制御回路
EXOR1 排他的論理和回路
INV1、INV10〜INV1m、INV21〜INV2m、INV31〜INV34 インバータ回路
NAND1、NAND11〜NAND1m、NAND31、32 NAND回路
NOR31 NOR回路
SEL1 セレクタ
TG11〜TG1m、TG31 トランスファゲート
Claims (6)
- DLL(Delay Locked Loop)回路を備える半導体装置であって、
前記DLL回路は、
第1のクロック信号を遅延させて第2のクロック信号を生成する遅延部と、
前記第1のクロック信号と、前記第2のクロック信号をさらに遅延した信号との位相を比較する位相比較回路と、
前記遅延部の遅延量を決定するカウント値を前記遅延部に出力すると共に、前記位相比較回路の位相比較結果に応じてアップダウンするカウンタ回路と、
初期設定動作時において、前記第1のクロック信号の周期を検知し、検知した周期に応じた前記カウント値の初期値を前記カウンタ回路に対して出力する初期遅延量制御回路と、
を備えることを特徴とする半導体装置。 - 前記初期遅延量制御回路は、前記第1のクロック信号の周期に比例したパルス幅を有するパルス信号を発生するパルス信号発生部と、
前記パルス信号を遅延させる縦列接続された複数の遅延素子と、
前記パルス信号の前記パルス幅内に前記パルス信号が前記複数の遅延素子の何段目まで進んだかを検知する検知部と、
前記検知部における検知結果に基づいて前記カウント値の初期値を発生するコード発生部と、
を備えることを特徴とする請求項1に記載の半導体装置。 - 前記初期遅延量制御回路は、所定の時間内における前記第1のクロック信号のクロッキング回数をカウントし、該カウントの結果に基づいて前記カウント値の初期値を発生することを特徴とする請求項1に記載の半導体装置。
- 前記カウンタ回路は、2分探索法によってアップダウン動作を行うことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記カウンタ回路は、線形探索法によってアップダウン動作を行うことを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- リードコマンドに対応してデータを外部に出力する出力部を更に備え、前記第2のクロック信号は、前記出力部の出力タイミングを制御する信号であることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011094264A JP5932237B2 (ja) | 2011-04-20 | 2011-04-20 | 半導体装置 |
US13/451,131 US8643416B2 (en) | 2011-04-20 | 2012-04-19 | Semiconductor device including a delay locked loop circuit |
US14/152,488 US8917130B2 (en) | 2011-04-20 | 2014-01-10 | Semiconductor device including a delay locked loop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011094264A JP5932237B2 (ja) | 2011-04-20 | 2011-04-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012227779A true JP2012227779A (ja) | 2012-11-15 |
JP5932237B2 JP5932237B2 (ja) | 2016-06-08 |
Family
ID=47020838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011094264A Active JP5932237B2 (ja) | 2011-04-20 | 2011-04-20 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8643416B2 (ja) |
JP (1) | JP5932237B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021112000A1 (ja) * | 2019-12-05 | 2021-06-10 | ローム株式会社 | Pll回路およびその制御方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20120111074A (ko) * | 2011-03-31 | 2012-10-10 | 에스케이하이닉스 주식회사 | 내부 클럭 신호 생성 회로 및 그의 동작 방법 |
US8471611B2 (en) * | 2011-11-04 | 2013-06-25 | Broadcom Corporation | Fractional-N phase locked loop based on bang-bang detector |
US9413568B2 (en) | 2013-09-27 | 2016-08-09 | Cavium, Inc. | Method and apparatus for calibrating an input interface |
US9496012B2 (en) * | 2013-09-27 | 2016-11-15 | Cavium, Inc. | Method and apparatus for reference voltage calibration in a single-ended receiver |
CN105204602B (zh) * | 2015-09-02 | 2018-06-22 | 上海兆芯集成电路有限公司 | 电源控制装置 |
US9768757B1 (en) * | 2016-06-08 | 2017-09-19 | Altera Corporation | Register circuitry with asynchronous system reset |
CN107463714A (zh) * | 2017-08-24 | 2017-12-12 | 北京工业大学 | 一种基于证据链时间序列的关键证据二分搜索方法 |
US10964363B2 (en) * | 2018-08-14 | 2021-03-30 | Mediatek Inc. | Delay tracking method and memory system |
KR20210057416A (ko) * | 2019-11-12 | 2021-05-21 | 삼성전자주식회사 | 무선 통신 장치 및 방법 |
KR20210130434A (ko) | 2020-04-22 | 2021-11-01 | 삼성전자주식회사 | 지연 동기 루프 회로 및 이를 구비하는 반도체 메모리 장치 |
US11139019B1 (en) * | 2021-02-16 | 2021-10-05 | Micron Technology, Inc. | Apparatuses and methods for delay control error protection |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1022822A (ja) * | 1996-07-05 | 1998-01-23 | Sony Corp | ディジタルpll回路 |
JPH11273342A (ja) * | 1998-03-20 | 1999-10-08 | Fujitsu Ltd | 半導体装置 |
JPH11355131A (ja) * | 1998-06-11 | 1999-12-24 | Fujitsu Ltd | Dll回路 |
JP2002344310A (ja) * | 2001-05-16 | 2002-11-29 | Hitachi Ltd | クロック位相制御回路 |
JP2004086645A (ja) * | 2002-08-28 | 2004-03-18 | Renesas Technology Corp | マイクロコンピュータ |
US6917229B2 (en) * | 2002-11-27 | 2005-07-12 | Hynix Semiconductor Inc. | Delay locked loop having low jitter in semiconductor device |
WO2005117259A1 (ja) * | 2004-05-26 | 2005-12-08 | Matsushita Electric Industrial Co., Ltd. | スキュー補正装置 |
US20060087353A1 (en) * | 2004-10-27 | 2006-04-27 | Alessandro Minzoni | Method and apparatus compensating for frequency drift in a delay locked loop |
JP2009177778A (ja) * | 2008-01-25 | 2009-08-06 | Elpida Memory Inc | Dll回路及びこれを用いた半導体装置、並びに、dll回路の制御方法 |
JP2009194902A (ja) * | 2008-02-14 | 2009-08-27 | Hynix Semiconductor Inc | 位相同期装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001339294A (ja) * | 2000-05-30 | 2001-12-07 | Mitsubishi Electric Corp | Dll回路 |
US6909311B2 (en) * | 2002-04-03 | 2005-06-21 | Analog Devices, Inc. | Methods and apparatus for synthesizing a clock signal |
US7265594B2 (en) * | 2002-04-03 | 2007-09-04 | Analog Devices, Inc. | Methods and apparatus for generating timing signals |
US6633190B1 (en) * | 2002-04-26 | 2003-10-14 | Intel Corporation | Multi-phase clock generation and synchronization |
US6836166B2 (en) * | 2003-01-08 | 2004-12-28 | Micron Technology, Inc. | Method and system for delay control in synchronization circuits |
US7002384B1 (en) * | 2004-01-16 | 2006-02-21 | Altera Corporation | Loop circuitry with low-pass noise filter |
US7190201B2 (en) * | 2005-02-03 | 2007-03-13 | Mosaid Technologies, Inc. | Method and apparatus for initializing a delay locked loop |
US7616708B2 (en) * | 2006-04-17 | 2009-11-10 | Novatek Microelectronics Corp. | Clock recovery circuit |
US7433262B2 (en) * | 2006-08-22 | 2008-10-07 | Atmel Corporation | Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction |
KR100956770B1 (ko) | 2007-12-10 | 2010-05-12 | 주식회사 하이닉스반도체 | Dll 회로 및 그 제어 방법 |
JP5641697B2 (ja) | 2009-02-12 | 2014-12-17 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | クロック制御回路及びこれを備える半導体装置 |
JP2011061457A (ja) * | 2009-09-09 | 2011-03-24 | Elpida Memory Inc | クロック生成回路及びこれを備える半導体装置並びにデータ処理システム |
JP2013021396A (ja) * | 2011-07-07 | 2013-01-31 | Elpida Memory Inc | 半導体装置及びその制御方法 |
JP2013183415A (ja) * | 2012-03-05 | 2013-09-12 | Elpida Memory Inc | 半導体装置及びクロック信号の位相調整方法 |
-
2011
- 2011-04-20 JP JP2011094264A patent/JP5932237B2/ja active Active
-
2012
- 2012-04-19 US US13/451,131 patent/US8643416B2/en active Active
-
2014
- 2014-01-10 US US14/152,488 patent/US8917130B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1022822A (ja) * | 1996-07-05 | 1998-01-23 | Sony Corp | ディジタルpll回路 |
JPH11273342A (ja) * | 1998-03-20 | 1999-10-08 | Fujitsu Ltd | 半導体装置 |
JPH11355131A (ja) * | 1998-06-11 | 1999-12-24 | Fujitsu Ltd | Dll回路 |
JP2002344310A (ja) * | 2001-05-16 | 2002-11-29 | Hitachi Ltd | クロック位相制御回路 |
JP2004086645A (ja) * | 2002-08-28 | 2004-03-18 | Renesas Technology Corp | マイクロコンピュータ |
US6917229B2 (en) * | 2002-11-27 | 2005-07-12 | Hynix Semiconductor Inc. | Delay locked loop having low jitter in semiconductor device |
WO2005117259A1 (ja) * | 2004-05-26 | 2005-12-08 | Matsushita Electric Industrial Co., Ltd. | スキュー補正装置 |
US20060087353A1 (en) * | 2004-10-27 | 2006-04-27 | Alessandro Minzoni | Method and apparatus compensating for frequency drift in a delay locked loop |
JP2009177778A (ja) * | 2008-01-25 | 2009-08-06 | Elpida Memory Inc | Dll回路及びこれを用いた半導体装置、並びに、dll回路の制御方法 |
JP2009194902A (ja) * | 2008-02-14 | 2009-08-27 | Hynix Semiconductor Inc | 位相同期装置 |
Non-Patent Citations (1)
Title |
---|
JPN6015037349; Bo Ye, et al.: 'A Fast-lock Digital Delay-Locked Loop Controller' ASIC, 2009. ASICON '09. IEEE 8th International Conference on , 20091020, pp.809 - 812, IEEE * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021112000A1 (ja) * | 2019-12-05 | 2021-06-10 | ローム株式会社 | Pll回路およびその制御方法 |
Also Published As
Publication number | Publication date |
---|---|
US20120268181A1 (en) | 2012-10-25 |
US20140125387A1 (en) | 2014-05-08 |
US8643416B2 (en) | 2014-02-04 |
JP5932237B2 (ja) | 2016-06-08 |
US8917130B2 (en) | 2014-12-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5932237B2 (ja) | 半導体装置 | |
JP4190662B2 (ja) | 半導体装置及びタイミング制御回路 | |
US7813215B2 (en) | Circuit and method for generating data output control signal for semiconductor integrated circuit | |
KR100305546B1 (ko) | 반도체장치,반도체시스템및디지탈지연회로 | |
US7864623B2 (en) | Semiconductor device having latency counter | |
JP3993717B2 (ja) | 半導体集積回路装置 | |
US7394722B2 (en) | Method for controlling data output timing of memory device and device therefor | |
JP5451012B2 (ja) | Dll回路及びその制御方法 | |
KR102662555B1 (ko) | 지연 동기 루프 회로 및 이를 구비하는 반도체 메모리 장치 | |
JP3481065B2 (ja) | 位相比較回路および半導体集積回路 | |
JP3335537B2 (ja) | 半導体集積回路 | |
JPH10171774A (ja) | 半導体集積回路 | |
US9154141B2 (en) | Continuous high-frequency event filter | |
JP2006190441A (ja) | 同期式半導体装置用のレイテンシ制御装置及びレイテンシ制御方法 | |
JP2009211797A (ja) | 半導体素子 | |
JP2013069360A (ja) | 半導体装置及びデータ処理システム | |
JP2010287304A (ja) | 半導体メモリ装置および出力イネーブル信号生成方法 | |
JP5675035B2 (ja) | Zqキャリブレーション回路 | |
US8729940B2 (en) | Delay locked loop circuit and semiconductor device having the same | |
KR102075497B1 (ko) | 반도체 집적회로 | |
JP2008059735A (ja) | 半導体メモリ装置及びその駆動方法 | |
CN110349606B (zh) | 半导体存储器件及其操作方法 | |
JP2015012350A (ja) | 半導体装置 | |
JP2014033414A (ja) | 半導体装置 | |
KR100762882B1 (ko) | 데이터 출력 인에이블 신호 제어 회로 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130730 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140401 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20150327 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20150330 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150526 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150825 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150915 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20151214 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160315 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160412 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160428 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5932237 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |