JP2012064826A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2012064826A
JP2012064826A JP2010208814A JP2010208814A JP2012064826A JP 2012064826 A JP2012064826 A JP 2012064826A JP 2010208814 A JP2010208814 A JP 2010208814A JP 2010208814 A JP2010208814 A JP 2010208814A JP 2012064826 A JP2012064826 A JP 2012064826A
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Prior art keywords
semiconductor
layer
semiconductor device
semiconductor substrate
chip
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JP2010208814A
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JP5714280B2 (ja
Inventor
Yuichi Watanabe
雄一 渡辺
Akira Yamane
彰 山根
Yasuo Oishibashi
康雄 大石橋
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On Semiconductor Trading Ltd
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On Semiconductor Trading Ltd
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Priority to JP2010208814A priority Critical patent/JP5714280B2/ja
Priority to CN201110261212.1A priority patent/CN102412226B/zh
Priority to US13/229,079 priority patent/US8896108B2/en
Publication of JP2012064826A publication Critical patent/JP2012064826A/ja
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Publication of JP5714280B2 publication Critical patent/JP5714280B2/ja
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Abstract

【課題】リードフレーム上に半導体チップが載置された半導体装置において、サージに対する耐性の向上を図る。
【解決手段】ＩＣチップ１０Ａを構成するＰ型の半導体基板１０の表面には、Ｎ型の埋め込み層１１及びエピタキシャル層１２と、Ｐ型の半導体層１３が配置されている。半導体基板１０の裏面には金属薄膜３０が配置され、その金属薄膜３０と、金属のアイランド５１の間には銀粒子等を含む導電性ペースト４０が挟まれている。半導体層１３の表面に配置されたパッド電極１６にサージが印加されると、半導体層１３から半導体基板１０に流れるサージ電流は、金属薄膜３０を通って金属のアイランド５１に向かう。
【選択図】図３

Description

本発明は、半導体装置に関し、特に、リードフレーム上に半導体チップが載置された半導体装置に関する。
複数のＩＣチップ等の半導体チップを備えた半導体装置では、例えば図６に示すように、ＩＣチップ１１０Ａは、銅等の金属からなるリードフレームのアイランド１５０上に、導電性ペースト１４０を介してダイボンドされる。
リードフレーム上に半導体チップが載置された半導体装置については、例えば特許文献１，２に開示されている。
特開２０１０−８０９１４号公報 特開２００６−３２４７９号公報
しかしながら、半導体装置の使用目的によっては、図６に示すように、ＩＣチップ１１０Ａの表面に配置されたパッド電極１１１から、サージ（振幅の立ち上がりの大きいパルス状の過電圧）が印加されやすくなる。例えば、半導体装置が車載の点火プラグを制御するイグナイタである場合、その周囲のモーター等の他の車載機器から生じるノイズを起因として大きなサージが印加されやすい。
サージの大きさによっては、パッド電極１１１から半導体基板１１０の中に流れたサージ電流が、半導体基板１１０の裏面に到達し、絶縁破壊を生じさせる場合があった。そして、その際に生じた熱により、半導体基板１１０にクラックが生じて、イグナイタが故障してしまう場合があった。
そこで本発明は、リードフレーム上に半導体チップが載置された半導体装置において、サージに対する耐性の向上を図るものである。
本発明は、リードフレームのアイランド上に半導体チップがダイボンドされた半導体装置であって、前記半導体チップは、第１導電型の半導体基板、前記半導体基板の表面に配置された第２導電型の第１の半導体層、及び前記第１の半導体層の表面に配置された第１導電型の第２の半導体層からなる寄生バイポーラトランジスタと、前記第２の半導体層の表面に形成されたパッド電極と、前記半導体基板の裏面と直接接して該裏面を覆う金属薄膜と、を備え、前記金属薄膜と前記アイランドとの間には、導電性ペーストが配置されていることを特徴とする。
本発明によれば、金属のリードフレーム上に半導体チップが載置された半導体装置において、サージに対する耐性を向上することができる。
本発明の実施形態による半導体装置とその周辺回路を示す回路図である。 本発明の実施形態による半導体装置の概略構成を示す平面図である。 本発明の実施形態による半導体装置を示す断面図である。 図３の半導体装置の金属薄膜の積層構造を示す断面図である。 比較例による半導体装置を示す断面図である。 従来例による半導体装置を示す断面図である。
本発明の実施形態による半導体装置について、図面を参照して説明する。図１は、この半導体装置とその周辺回路の概略構成を示す回路図である。この半導体装置は、サージ（例えば、振幅の立ち上がりの大きいパルス状の過電圧）が印加されやすい半導体装置であり、例えば、車載用のイグナイタ１であるものとする。図２は、図１のイグナイタ１の概略構成を示す平面図である。
図１に示すように、イグナイタ１は、車載のエンジンの点火プラグ２の発火を制御する機能を有し、複数の半導体チップ、例えば、制御回路として形成されたＩＣチップ１０Ａと、スイッチング素子であるＩＧＢＴチップ１０Ｂ等を備える。イグナイタ１は、ＩＣチップ１０ＡによってＩＧＢＴチップ１０Ｂのスイッチング動作を制御し、電源から点火コイルの１次コイル３Ａに流れる電流をＩＧＢＴチップ１０Ｂで遮断することにより自己誘導を生じさせ、点火コイルの２次コイル３Ｂに高電圧を発生させる。この高電圧が点火プラグ２に印加されることで発火が行われる。
車載のイグナイタ１では、車載のモーター等の他の機器から生じるノイズを起因とした大きなサージが、電源端子Ｔ１や配線を介して、ＩＣチップ１０Ａに印加されやすい。特に、自動車のエンジン停止に伴ってサージが発生しやすい。
イグナイタ１を構成するＩＣチップ１０ＡとＩＧＢＴチップ１０Ｂは、例えば図２に示すように、銅等の金属からなるリードフレーム５０，６０の各アイランド５１，６１上にそれぞれダイボンドされ、必要に応じて不図示の樹脂により封止される。なお、図の例では、ＩＣチップ１０ＡとＩＧＢＴチップ１０Ｂは、ボンディングワイヤ７１を介して、リード端子７２と接続されている。複数のリード端子７２の中の１つは、例えば電源と接続された電源端子Ｔ１として形成される。また、２つのアイランド５１，６１の間には、それらを接続するチップコンデンサ４が配置されている。
以下に、リードフレーム５０のアイランド５１にダイボンドされたＩＣチップ１０Ａについて図面を参照して説明する。図３は、イグナイタ１の中のＩＣチップ１０Ａを示す断面図である。なお、図３では、イグナイタ１に形成される保護抵抗層の形成領域とその近傍を簡略化して示し、他の構成要素、例えばトランジスタの形成領域については図示を省略している。また、図４は、図３の金属薄膜３０の積層構造を示す拡大断面図である。
図３に示すように、ＩＣチップ１０Ａは、Ｐ型のシリコン基板である半導体基板１０によって構成される。半導体基板１０の表面において、Ｎ型の埋め込み層１１が配置され、その上層にＮ型のエピタキシャル層１２が配置されている。エピタキシャル層１２の表面の一部にはＰ型の半導体層１３が配置されている。なお、図の例では、埋め込み層１１の両端は、ＩＣチップ１０Ａの表面まで延びている。その埋め込み層１１の両端の外側にはエピタキシャル層１２が存在し、そのエピタキシャル層１２の外側には、半導体基板１０の表面と接続されたＰ型の素子分離層１４が配置されている。
本実施形態の半導体層１３は、所定の抵抗値Ｒによってサージ電流を弱めるためのイグナイタ１の保護抵抗層として用いられるものとする。この場合、半導体層１３の表面の一方の端は、絶縁膜１５の開口部を通してパッド電極１６と接続されている。パッド電極１６は、図１の電源端子１と接続されたボンディングワイヤ７１を介して、電源に接続されている。半導体層１３の他方の端は、絶縁膜１５の開口部を通して配線１７と接続されている。配線１７は不図示の他の素子と接続されている。また、素子分離層１４には、接地された配線１８が絶縁膜１５の開口部を通して接続されている。
ＩＣチップ１０Ａの裏面側では、半導体基板１０の裏面と直接接して、該裏面を覆う金属薄膜３０が配置されている。金属薄膜３０は、半導体基板１０の裏面全体を覆っていることが好ましい。金属薄膜３０とアイランド５１の間には、導電性粒子と樹脂からなる導電性ペースト４０が配置されている。導電性ペースト４０は、金属薄膜３０と直接接すると共に、接地されたアイランド５１と直接接して配置されている。
導電性ペースト４０は、導電性粒子として銀粒子を含む銀ペーストであることが好ましい。銀ペーストを用いたダイボンドによれば、他の材料、例えば無鉛半田を用いたダイボンドに比して、ボンディング時の加工温度を下げることができ、また、製造コストを低く抑える利点がある。
なお、ＩＣチップの製造工程において、半導体基板１０の裏面には、例えばバックグラインド後に、シリコン基板である半導体基板１０の酸化により自然に形成される酸化膜、即ち自然酸化膜（不図示）が形成される。金属薄膜３０は、この自然酸化膜を例えばプラズマエッチング処理により除去した直後に、例えば蒸着法によって半導体基板１０の裏面に形成される。これにより、半導体基板１０の裏面と金属薄膜３０は、自然酸化膜を介さずに直接接する形になり、半導体基板１０からアイランド５１に安定して、電流を流すことができる。
図４に示すように、金属薄膜３０は、ＩＣチップ１０Ａの裏面、即ち半導体基板１０の裏面側から、半導体基板１０の裏面に直接接して形成されたアルミニウム層３１、さらにクロム層３２、銅層３３、金層３４がこの順で積層されたものである。アルミニウム層３１は、半導体基板１０との接触を良好にし、クロム層３２は、アルミニウム層３１と銅層３３の相互反応を防止し、銅層３３は金属薄膜３０全体の電気抵抗を低減させ、金層３４は銅層３３表面の酸化を防止する。金層３４は、導電性粒子４１（好ましくは銀粒子）と樹脂４２を含む導電性ペースト４０と直接接している。この金属薄膜３０は、全体で例えば約０．５μｍ〜１．５μｍの膜厚を有している。
このＩＣチップ１０Ａには、図３の断面構成から分かるように、Ｐ型の半導体基板１０をコレクタ、Ｎ型の埋め込み層１１及びエピタキシャル層１２をベース、Ｐ型の半導体層１３をエミッタとしたＰＮＰバイポーラトランジスタ、即ち寄生トランジスタＴｒｐが形成される。
そして、ボンディングワイヤ７１とパッド電極１６を介して半導体層１３に印加されたサージの電位が、寄生トランジスタＴｒｐをブレークダウンさせるほど大きな場合には、半導体層１３から寄生トランジスタＴｒｐを通って、Ｐ型の半導体基板１０中にサージ電流が流れる。このサージ電流は、Ｐ型の素子分離層１４を通って、接地された配線１８に流れると共に（即ち第１のパス）、半導体基板１０の裏面から金属薄膜３０を通って、接地されたアイランド５１に流れる（即ち第２のパス）。
なお、上記サージが半導体層１３に印加されても、寄生トランジスタＴｒｐがブレークダウンしない場合には、サージ電流は半導体基板１０には流れず、保護抵抗層である半導体層１３の抵抗値Ｒに応じて弱められて配線１７に流れる。
ここで、上述したＩＣチップ１０Ａの構造に対する比較例として、半導体基板１０の裏面に金属薄膜３０が形成されない場合を考える。この場合、図５の断面図に示すように、半導体基板１０の裏面には、例えば半導体基板１０のバックグラインド後に、シリコン基板である半導体基板１０の酸化によって自然酸化膜１１０Ｆが形成されたままである。そして、この状態のまま、自然酸化膜１１０Ｆとアイランド５１との間に、導電性ペースト４０が挟まれる。
この自然酸化膜１１０Ｆは、半導体基板１０の裏面において一様な膜厚や状態では形成されず、局所的に、絶縁耐圧が低く絶縁破壊されやすい部分、例えば膜厚の薄い部分１１０Ｔを有して形成される。そのため、寄生トランジスタＴｒｐを通して半導体基板１０にサージ電流が流れる場合、自然酸化膜１１０Ｆの絶縁破壊されやすい部分１１０Ｔでは、電流密度の大きなサージ電流によって絶縁破壊が起こる。その際に生じる熱によって、半導体基板１０にクラック１０ＣＬが生じ、ＩＣチップ１０Ａが損傷してしまう。このクラック１０ＣＬは、半導体基板１０から、パッド電極１６と重畳する半導体層１３の中まで延びる場合もあり、さらには、パッド電極１６と半導体層１３の界面まで延びて、ＩＣチップ１０Ａを貫通する場合もある。
これに対して本実施形態のＩＣチップ１０Ａによれば、寄生トランジスタＴｒｐを通ってＰ型の半導体基板１０中に流れたサージ電流は、Ｐ型の素子分離層１４と接地された配線１８に向かう第１のパスに加えて、さらに、半導体基板１０の裏面から金属薄膜３０を通って、接地されたアイランドに向かう第２のパスに流れるため、自然酸化膜１１０Ｆの絶縁破壊によって半導体基板１０等にクラック１０ＣＬが生じることなく、ＩＣチップ１０Ａの損傷を防止することができる。特に、金属薄膜３０が半導体基板１０の裏面の全体を覆って形成される場合、第２のパスが広くなって、より確実に、サージ電流を半導体基板１０からアイランド５１に導くことができる。
なお、本発明は上記実施形態に限定されず、その要旨を逸脱しない範囲で変更が可能なことはいうまでもない。
例えば、上記実施形態では、ＩＣチップ１０Ａの半導体層１３が、イグナイタ１の保護抵抗層である場合について説明したが、本発明はこれに限定されず、他の素子、例えばトランジスタの形成領域についても適用される。この場合、トランジスタは、少なくともＰ型の半導体基板１０、Ｎ型の埋め込み層１１とエピタキシャル層１２、Ｐ型の半導体層１３を用いて形成される。
また、上記実施形態の半導体装置は車載のイグナイタ１であるものとしたが、本発明はこれに限定されず、サージが印加されやすいものであれば、他の車載半導体装置に対しても適用される。
１ イグナイタ ２ 点火プラグ
３Ａ １次コイル ３Ｂ ２次コイル
４ チップコンデンサ
１０Ａ ＩＣチップ １０Ｂ ＩＧＢＴチップ
１０ 半導体基板 １１ 埋め込み層
１２ エピタキシャル層 １３ 半導体層
１４ 素子分離層 １５ 絶縁膜
１６ パッド電極 １７，１８ 配線
３０ 金属薄膜 ３１ アルミニウム層
３２ クロム層 ３３ 銅層
３４ 金層 ４０ 導電性ペースト
５０，６０ リードフレーム ５１，６１ アイランド
７１ ボンディングワイヤ ７２ リード端子

Claims (7)

  1. リードフレームのアイランド上に半導体チップがダイボンドされた半導体装置であって、
    前記半導体チップは、
    第１導電型の半導体基板、前記半導体基板の表面に配置された第２導電型の第１の半導体層、及び前記第１の半導体層の表面に配置された第１導電型の第２の半導体層からなる寄生バイポーラトランジスタと、
    前記第２の半導体層の表面に形成されたパッド電極と、
    前記半導体基板の裏面と直接接して該裏面を覆う金属薄膜と、を備え、
    前記金属薄膜と前記アイランドとの間には、導電性ペーストが配置されていることを特徴とする半導体装置。
  2. 前記金属薄膜は、前記半導体基板の裏面側から、アルミニウム層、クロム層、銅層、金層がこの順で積層されてなることを特徴とする請求項１に記載の半導体装置。
  3. 前記導電性ペーストは、銀粒子を含む銀ペーストであることを特徴とする請求項１又は請求項２に記載の半導体装置。
  4. 前記第２の半導体層は、前記パッド電極を介して前記半導体チップに印加されるサージに対する保護抵抗層であることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。
  5. 前記パッド電極は、電源と接続されていることを特徴とする請求項１乃至請求項４のいずれかに記載の半導体装置。
  6. 前記半導体装置は、車載向け半導体装置であることを特徴とする請求項１乃至５のいずれかに記載の半導体装置。
  7. 前記半導体装置は、イグナイタ向け半導体装置であることを特徴とする請求項１乃至６のいずれかに記載の半導体装置。
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