JP7301009B2 - 半導体装置、および半導体装置の製造方法 - Google Patents
半導体装置、および半導体装置の製造方法 Download PDFInfo
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- JP7301009B2 JP7301009B2 JP2020020476A JP2020020476A JP7301009B2 JP 7301009 B2 JP7301009 B2 JP 7301009B2 JP 2020020476 A JP2020020476 A JP 2020020476A JP 2020020476 A JP2020020476 A JP 2020020476A JP 7301009 B2 JP7301009 B2 JP 7301009B2
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Description
図1は、本実施の形態1による半導体装置の構成の一例を示す断面図である。
図4は、本実施の形態2による半導体装置の構成の一例を示す断面図である。図5は、図4に示す半導体装置の平面図である。
図6は、本実施の形態3による半導体装置を構成する回路の一例を示す図である。図7は、図6に示す半導体装置の平面図である。
Claims (7)
- 絶縁基板と、
前記絶縁基板上に設けられた回路パターンと、
前記絶縁基板上であって前記回路パターンと平面視で離間して設けられたスナバ回路用基板と、
前記回路パターンおよび前記スナバ回路用基板のうちの一方に設けられた抵抗と、
前記回路パターンおよび前記スナバ回路用基板のうちの他方に設けられたコンデンサと、
前記抵抗および前記コンデンサと電気的に接続された半導体素子と、
を備え、
前記スナバ回路用基板は、前記絶縁基板に接する絶縁層を含み、
前記回路パターンは、P極と同電位であるP側回路パターンと、N極と同電位であるN側回路パターンとを含む、半導体装置。 - 前記抵抗は、前記スナバ回路用基板に設けられ、
前記コンデンサは、前記回路パターンに設けられる、請求項1に記載の半導体装置。 - 前記回路パターンにおいて、当該回路パターンに設けられた前記抵抗または前記コンデンサと並列に設けられた配線をさらに備える、請求項1または2に記載の半導体装置。
- 前記半導体素子は、複数存在し、
前記抵抗および前記コンデンサは、少なくとも1つの前記半導体素子に接続されることを特徴とする、請求項1から3のいずれか1項に記載の半導体装置。 - 前記半導体素子は、炭化珪素を含む、請求項1から4のいずれか1項に記載の半導体装置。
- 前記スナバ回路用基板は、前記絶縁層上に設けられたスナバ回路パターンを有し、
前記抵抗または前記コンデンサは、前記スナバ回路パターン上に設けられる、請求項1から5のいずれか1項に記載の半導体装置。 - 請求項1から6のいずれか1項に記載の半導体装置の製造方法であって、
(a)前記抵抗または前記コンデンサが設けられた前記スナバ回路用基板単体に対して絶縁耐圧試験を実施する工程と、
(b)前記工程(a)の後、前記スナバ回路用基板を前記絶縁基板上に設け、前記スナバ回路用基板と前記回路パターンとを電気的に接続する工程と、
(c)前記工程(b)の後、前記抵抗および前記コンデンサからなるスナバ回路に対して絶縁耐圧試験を実施する工程と、
を備える、半導体装置の製造方法。
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