CN115799208A - 功率半导体模块 - Google Patents
功率半导体模块 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 239000011888 foil Substances 0.000 claims abstract description 107
- 239000004020 conductor Substances 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
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Abstract
本发明涉及功率半导体模块,其具有包括至少一个基底的基底布置结构、功率半导体组件、包括至少一个箔堆叠件的箔堆叠布置结构和导电桥接元件,相应的基底包括基底导体迹线,功率半导体组件布置在基底导体迹线上并与其导电接触,相应的箔堆叠件包括箔堆叠导体迹线,功率半导体组件通过基底导体迹线和箔堆叠导体迹线彼此导电连接以形成电路,导电桥接元件包括远离箔堆叠布置结构延伸的第一和第二接触区段和将其彼此导电连接的连接区段,第一接触区段与第一基底导体迹线或箔堆叠导体迹线导电接触,第二接触区段与第二基底导体迹线或箔堆叠导体迹线导电接触,桥接元件至少与箔堆叠布置结构的箔堆叠导体迹线的一个区段并联电连接。
Description
技术领域
本发明涉及一种功率半导体模块,其具有基底布置结构、功率半导体组件和箔堆叠布置结构。
背景技术
DE 10 2017 115 883 A1公开了一种功率半导体模块,其具有基底布置结构、功率半导体组件和箔堆叠布置结构。功率半导体组件借助于基底布置结构的基底导体迹线和箔堆叠布置结构的箔堆叠导体迹线彼此导电连接,以便形成电路。
在这种情况下的缺点是,当大的电流流动通过箔堆叠布置结构的箔堆叠导体迹线中的至少一个时,这可能导致所涉及的至少一个导体迹线的强烈加热。该至少一个导体迹线的加热可能导致热量输入到布置在该至少一个导体迹线附近的功率半导体组件中,使得它们只能以降低的电功率操作。
DE 10 2005 039 278 A1公开了一种具有功率组件的功率半导体模块,该功率组件将功率半导体模块的不同基底的两个导体迹线彼此导电地连接,该两个导体迹线布置在基底上。
发明内容
本发明的目的是提供一种功率半导体模块,其具有基底布置结构、功率半导体组件和箔堆叠布置结构,其中从箔堆叠布置结构输入到至少一个功率半导体组件中的热量被减少。
该目的通过一种功率半导体模块来实现,该功率半导体模块具有基底布置结构、功率半导体组件和箔堆叠布置结构,所述基底布置结构包括至少一个基底,其中相应的基底包括非导电绝缘层和布置在绝缘层上的基底导体迹线,所述功率半导体组件布置在基底布置结构的基底导体迹线上并与其导电接触,所述箔堆叠布置结构包括至少一个箔堆叠件,其中相应的箔堆叠件包括被构造成形成箔堆叠导体迹线的第一导电箔和第二导电箔以及布置在第一导电箔与第二导电箔之间的非导电绝缘箔,其中功率半导体组件借助于基底布置结构的基底导体迹线和箔堆叠布置结构的箔堆叠导体迹线而彼此导电连接以形成电路,并且该功率半导体模块具有导电桥接元件,该导电桥接元件包括远离箔堆叠布置结构延伸的第一接触区段和第二接触区段以及将第一接触区段和第二接触区段彼此导电连接的连接区段,其中第一接触区段与基底布置结构的第一基底导体迹线导电接触或与箔堆叠布置结构的箔堆叠导体迹线导电接触,并且第二接触区段与基底布置结构的第二基底导体迹线导电接触或与箔堆叠布置结构的箔堆叠导体迹线导电接触,其中桥接元件至少与箔堆叠布置结构的箔堆叠导体迹线的一个区段并联电连接。
已经发现有利的是,将桥接元件构造为金属片。以这种方式,桥接元件具有低电感并且可以经济地生产。
此外还发现有利的是,连接区段具有从150μm到1000μm、特别优选地从500μm到750μm的厚度。以这种方式,桥接元件具有特别低的电感。
此外,还发现有利的是,连接区段与第一接触区段和第二接触区段形成为一件。以这种方式,可以特别经济地生产桥接元件。
此外,已经发现有利的是,功率半导体模块包括用于与外部元件导电连接的负载端子元件,负载端子元件与桥接元件形成为一件。以这种方式,负载端子元件可以与桥接元件一起特别经济地生产。
在此情况下,已经发现有利的是,将负载端子元件配置为DC电位负载端子元件,该DC电位负载端子元件在功率半导体模块的操作期间具有DC电位。大的电流通常流动通过DC电位负载端子元件,使得该电流的一部分经由桥接元件流动。
此外发现有利的是,第一接触区段布置在负载端子元件附近,并且其导电地连接到负载端子元件。由于第一接触区段和负载端子元件之间的距离短,所以第一接触区段以低电感导电地连接到负载端子元件。
还发现有利的是,第一接触区段布置在基底布置结构的边缘区域中。以这种方式,电流可以从基底布置结构的任意位置、特别是从基底布置结构的中心区域,经由桥接元件传递到基底布置结构的边缘区域。
此外,已经发现有利的是,第一接触区段与基底布置结构的第一基底导体迹线导电接触或与箔堆叠布置结构的特定箔堆叠导体迹线导电接触,并且第二接触区段与基底布置结构的第二基底导体迹线导电接触或与箔堆叠布置结构的特定箔堆叠导体迹线导电接触,桥接元件至少与箔堆叠布置结构的特定箔堆叠导体迹线的一个区段并联电连接。以这种方式,特定箔堆叠导体迹线的该区段可以通过桥接元件以特别低的电感桥接。
已经进一步发现有利的是,将基底布置结构布置在功率半导体模块的基板上或功率半导体模块的散热器上。以这种方式,可以有效地耗散在功率半导体组件的操作期间在功率半导体组件中产生的热量。
附图说明
下面将参考附图解释本发明的示例性实施例,其中:
图1示出根据本发明的功率半导体模块的透视图;
图2示出根据本发明的功率半导体模块的透视图,其中未示出功率半导体模块的箔堆叠布置结构;
图3示出根据本发明的功率半导体模块的透视截面图;
图4示出根据本发明的功率半导体模块的区域的示意性截面图;以及
图5示出根据本发明的功率半导体模块的多个桥接元件的透视图。
具体实施方式
图1和图2分别示出根据本发明的功率半导体模块1的透视图,功率半导体模块1的箔堆叠布置结构3未在图2中示出。在图3中示出根据本发明的功率半导体模块1的透视截面图,在图4中示出根据本发明的功率半导体模块1的一区域的示意性截面图。在图5中示出根据本发明的功率半导体模块1的多个桥接元件9的透视图。
根据本发明的功率半导体模块1包括基底布置结构8,该基底布置结构8包括至少一个基底2,在此是单独的基底2,相应的基底2包括非导电绝缘层6和布置在绝缘层6上的基底导体迹线5a、5b、5c和5d。基底导体迹线5a、5b、5c和5d由布置在绝缘层6上的结构化金属层5形成。优选地,相应的基底5包括导电的、优选地未结构化的另外的金属层4,绝缘层6布置在金属层5和另外的金属层4之间。绝缘层6可以例如被配置为陶瓷板。相应的基底5可以例如被配置为直接铜结合基底(DCB基底)、被配置为活性金属钎焊基底(AMB基底)或被配置为绝缘金属基底(IMS)。
功率半导体模块1还包括布置在基底布置结构8的基底导体迹线5c和5d上并与其导电接触的功率半导体组件7。相应的功率半导体组件7包括半导体体部7a、前侧端子金属化部7b和后侧端子金属化部7c(参见图4)。相应的功率半导体组件7借助于相应的连接层15导电接触,连接层15可以例如被配置为焊料层或烧结层,其中基底导体迹线5c或5d被分配给相应的功率半导体组件7。
相应的功率半导体元件7优选为功率半导体开关或二极管的形式。在这种情况下,功率半导体开关通常为晶体管的形式,例如IGBT(绝缘栅双极晶体管)或MOSFET(金属氧化物半导体场效应晶体管),或为晶闸管的形式。
功率半导体模块1还包括箔堆叠布置结构3,其包括至少一个箔堆叠件10,在此是单独的箔堆叠件10,相应的箔堆叠件10包括被构造成形成箔堆叠导体迹线12a、12b、12c、13a、13b的第一导电箔12和第二导电箔13以及布置在第一导电箔12和第二导电箔13之间的不导电绝缘箔14。特别地,面向基底布置结构8的箔堆叠导体迹线12a、12b和12c也可以仅以用于箔堆叠布置结构3的电接触的接触区段的形式存在。导电的第一箔12和第二箔13或它们的箔堆叠导体迹线优选地通过延伸穿过绝缘箔14的导电贯通触点16彼此导电连接。功率半导体元件7通过基底布置结构8的基底导体迹线和箔堆叠布置结构3的箔堆叠导体迹线彼此导电连接,以便形成电路,在此以便形成彼此并联电互连的三个半桥电路。面向基底布置结构8的相应的箔堆叠导体迹线12a、12b或12c借助于相应的连接层15(其可以例如被配置为焊料层或烧结层)导电地接触到分配给相应的箔堆叠导体迹线的功率半导体组件7和/或导电地接触到分配给相应的箔堆叠导体迹线的基底导体迹线5a或5b。
功率半导体模块1还包括导电桥接元件9,该导电桥接元件9包括远离箔堆叠布置结构3延伸的第一接触区段9a和第二接触区段9b以及将第一接触区段9a和第二接触区段9b彼此导电连接的连接区段9c。在图5中,第一接触区段9a和连接区段9c之间的虚拟边界由虚线18表示,第二接触区段9b和连接区段9c之间的虚拟边界由虚线21表示。
在示例性实施例的范围内,功率半导体模块1包括多个桥接元件9。如在示例性实施例中那样,桥接元件9可以彼此导电连接,并且特别地,桥接元件9可以彼此形成为一件。在图5中,桥接元件9之间的虚拟边界通过虚线23和24表示。
如在示例性实施例中那样,第一接触区段9a与基底布置结构8的第一基底导体迹线5a或与箔堆叠布置结构3的箔堆叠导体迹线导电接触。如在示例性实施例中那样,第二接触区段9b与基底布置结构8的第二基底导体迹线5b或与箔堆叠布置结构3的箔堆叠导体迹线导电接触。桥接元件9至少与箔堆叠布置结构3的箔堆叠导体迹线13a的区段13a'并联电连接。桥接元件9与基底布置结构8或与箔堆叠布置结构3的相应导电接触可以例如被配置为焊接、钎焊或烧结连接。在这种情况下,应当注意,与第一接触区段9a导电接触的箔导体迹线、以及与第二接触区段9b导电接触的箔导体迹线、以及桥接元件9至少与该箔导体迹线的一部分并联电连接的箔导体迹线可以是多达三个不同的箔导体迹线。但是,其优选地是同一箔导体迹线,使得优选地第一接触区段9a与基底布置结构8的第一基底导体迹线5a或与箔堆叠布置结构3的特定箔堆叠导体迹线13a导电接触,并且第二接触区段9b与基底布置结构8的第二基底导体迹线5b或与箔堆叠布置结构3的特定箔堆叠导体迹线13a导电接触,桥接元件9至少与箔堆叠布置结构3的特定箔堆叠导体迹线13a的区段13a'并联电连接。
在没有桥接元件9的情况下,流动通过箔堆叠导体迹线13a的区段13a'的相对大的负载电流将导致箔堆叠导体迹线13a的强烈加热,并因此导致热量输入到箔堆叠导体迹线13a的紧邻区域中,特别是输入到在箔堆叠导体迹线13a下方与箔堆叠导体迹线13a齐平布置的功率半导体组件7中,使得它们只能以降低的电功率操作。由于桥接元件9,负载电流的一部分不再流动通过箔堆叠导体迹线13a的区段13a',而是流动通过桥接元件9,使得箔堆叠导体迹线13a被较少地加热,并且因此输入到布置在箔堆叠导体迹线13a附近的功率半导体组件7中的热量减少,使得它们可以以更高的电功率操作,也就是说,在这些功率半导体组件中可能发生更高的电损耗,而不会发生这些功率半导体组件的过热。
桥接元件9优选地被构造为金属片。连接区段9c优选地具有从150μm至1000μm的厚度,特别优选地具有从500μm至750μm的厚度。
连接区段9c优选地与第一接触区段9a和第二接触区段9b形成为一件。
功率半导体模块1优选地包括用于导电连接到外部元件的负载端子元件17,负载端子元件17与桥接元件9形成为一件。
功率半导体模块1优选地包括用于导电连接到另一外部元件的另一负载端子元件18。在功率半导体模块1的操作期间,第一负载端子元件17优选地具有第一电极性,并且另外的负载端子元件18优选地具有第二电极性。第一极性可以是正的并且第二极性可以是负的,或反之亦然。负载端子元件17或另外的负载端子元件18分别优选地被配置为DC电位负载端子元件,使得其在功率半导体模块1的操作期间具有DC电位。
第一接触区段9a优选地布置在负载端子元件17附近并且导电地连接到负载端子元件。第一接触区段9a优选地布置在基底布置结构8的边缘区域中。
功率半导体模块1优选地包括又一个另外的负载端子元件19,其优选地在功率半导体模块1的操作期间具有交变的电极性,用于导电连接到又一个另外的外部元件。负载端子元件19被配置为AC电位负载端子元件,使得其在功率半导体模块1的操作期间具有AC电位。在示例性实施例的范围中,功率半导体模块1包括多个负载端子元件19。
在示例性实施例的范围内,如通过示例的方式在图3中所示,基底布置结构8布置在功率半导体模块1的散热器20上。散热器20优选地包括冷却销20a或冷却翅片。作为替代,基底布置结构8可以布置在功率半导体模块1的基板上。基板优选地旨在布置在散热器上。
Claims (11)
1.一种功率半导体模块,其具有基底布置结构(8)、功率半导体组件(7)、箔堆叠布置结构(3)以及导电桥接元件(9),所述基底布置结构(8)包括至少一个基底(2),其中相应的基底(2)包括非导电的绝缘层(6)和布置在绝缘层(6)上的基底导体迹线(5a,5b,5c,5d),所述功率半导体组件(7)布置在基底布置结构(8)的基底导体迹线(5c,5d)上并与其导电接触,所述箔堆叠布置结构(3)包括至少一个箔堆叠件(10),其中相应的箔堆叠件(10)包括被构造成形成箔堆叠导体迹线(12a,12b,12c,13a,13b)的第一导电箔(12)和第二导电箔(13),以及布置在第一导电箔(12)与第二导电箔(13)之间的非导电的绝缘箔(14),其中功率半导体组件(7)借助于基底布置结构(8)的基底导体迹线(5a,5b,5c,5d)和箔堆叠布置结构(3)的箔堆叠导体迹线(12a,12b,12c,13a,13b)而彼此导电连接,从而形成电路,所述导电桥接元件(9)包括远离箔堆叠布置结构(3)延伸的第一接触区段(9a)和第二接触区段(9b)以及将第一接触区段(9a)和第二接触区段(9b)彼此导电连接的连接区段(9c),其中第一接触区段(9a)与基底布置结构(8)的第一基底导体迹线(5a)导电接触或与箔堆叠布置结构(3)的箔堆叠导体迹线(13a)导电接触,并且第二接触区段(9b)与基底布置结构(8)的第二基底导体迹线(5b)导电接触或与箔堆叠布置结构(3)的箔堆叠导体迹线(13a)导电接触,其中桥接元件(9)至少与箔堆叠布置结构(3)的箔堆叠导体迹线(13a)的一个区段(13a’)并联电连接。
2.根据权利要求1所述的功率半导体模块,其特征在于,桥接元件(9)构造为金属片。
3.根据前述权利要求之一所述的功率半导体模块,其特征在于,连接区段(9c)具有从150μm到1000μm的厚度。
4.根据权利要求1或2所述的功率半导体模块,其特征在于,连接区段(9c)与第一接触区段(9a)和第二接触区段(9b)形成为一件。
5.根据权利要求1或2所述的功率半导体模块,其特征在于,功率半导体模块(1)包括用于与外部元件导电连接的负载端子元件(17),所述负载端子元件(17)与桥接元件(9)形成为一件。
6.根据权利要求5所述的功率半导体模块,其特征在于,负载端子元件(17)配置为DC电位负载端子元件,该DC电位负载端子元件在功率半导体模块(1)的操作期间具有DC电位。
7.根据权利要求5所述的功率半导体模块,其特征在于,第一接触区段(9a)布置在负载端子元件(17)附近,并且其导电地连接到负载端子元件(17)。
8.根据权利要求1或2所述的功率半导体模块,其特征在于,第一接触区段(9a)布置在基底布置结构(8)的边缘区域。
9.根据权利要求1或2所述的功率半导体模块,其特征在于,第一接触区段(9a)与基底布置结构(8)的第一基底导体迹线(5a)导电接触或与箔堆叠布置结构(3)的特定箔堆叠导体迹线(13a)导电接触,并且第二接触区段(9b)与基底布置结构(8)的第二基底导体迹线(5b)或与箔堆叠布置结构(3)的特定箔堆叠导体迹线(13a)导电接触,桥接元件(9)至少与箔堆叠布置结构(3)的特定箔堆叠导体迹线(13a)的一个区段(13a’)并联电连接。
10.根据权利要求1或2所述的功率半导体模块,其特征在于,基底布置结构(8)布置在功率半导体模块(1)的基板上或功率半导体模块(1)的散热器(20)上。
11.根据权利要求3所述的功率半导体模块,其特征在于,连接区段(9c)具有从500μm到750μm的厚度。
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