JP2012009713A - 半導体パッケージおよび半導体パッケージの製造方法 - Google Patents

半導体パッケージおよび半導体パッケージの製造方法 Download PDF

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Publication number
JP2012009713A
JP2012009713A JP2010145550A JP2010145550A JP2012009713A JP 2012009713 A JP2012009713 A JP 2012009713A JP 2010145550 A JP2010145550 A JP 2010145550A JP 2010145550 A JP2010145550 A JP 2010145550A JP 2012009713 A JP2012009713 A JP 2012009713A
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Japan
Prior art keywords
resin layer
substrate
semiconductor chip
package
underfill resin
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Pending
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JP2010145550A
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English (en)
Japanese (ja)
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JP2012009713A5 (https=
Inventor
Takashi Ozawa
隆史 小澤
Kota Takeda
幸太 武田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010145550A priority Critical patent/JP2012009713A/ja
Priority to US13/168,126 priority patent/US20110316151A1/en
Publication of JP2012009713A publication Critical patent/JP2012009713A/ja
Publication of JP2012009713A5 publication Critical patent/JP2012009713A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07178—Means for aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2010145550A 2010-06-25 2010-06-25 半導体パッケージおよび半導体パッケージの製造方法 Pending JP2012009713A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010145550A JP2012009713A (ja) 2010-06-25 2010-06-25 半導体パッケージおよび半導体パッケージの製造方法
US13/168,126 US20110316151A1 (en) 2010-06-25 2011-06-24 Semiconductor package and method for manufacturing semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010145550A JP2012009713A (ja) 2010-06-25 2010-06-25 半導体パッケージおよび半導体パッケージの製造方法

Publications (2)

Publication Number Publication Date
JP2012009713A true JP2012009713A (ja) 2012-01-12
JP2012009713A5 JP2012009713A5 (https=) 2013-05-16

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JP2010145550A Pending JP2012009713A (ja) 2010-06-25 2010-06-25 半導体パッケージおよび半導体パッケージの製造方法

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Country Link
US (1) US20110316151A1 (https=)
JP (1) JP2012009713A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013239660A (ja) * 2012-05-17 2013-11-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US9013031B2 (en) 2013-06-18 2015-04-21 Samsung Electronics Co., Ltd. Semiconductor packages including heat diffusion vias and interconnection vias
KR20160090329A (ko) 2013-11-26 2016-07-29 토레이 엔지니어링 컴퍼니, 리미티드 실장 장치 및 실장 방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102351257B1 (ko) * 2014-07-07 2022-01-17 삼성전자주식회사 잔류응력을 갖는 반도체 패키지 및 그 제조방법
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213741A (ja) * 1996-01-31 1997-08-15 Hitachi Chem Co Ltd 半導体装置およびその製造方法
JP2000277564A (ja) * 1999-03-23 2000-10-06 Casio Comput Co Ltd 半導体装置及びその製造方法
JP2005311321A (ja) * 2004-03-22 2005-11-04 Sharp Corp 半導体装置およびその製造方法、並びに、該半導体装置を備えた液晶モジュールおよび半導体モジュール
US20050277231A1 (en) * 2004-06-14 2005-12-15 Hembree David R Underfill and encapsulation of semicondcutor assemblies with materials having differing properties and methods of fabrication using stereolithography
JP2010103129A (ja) * 2008-10-21 2010-05-06 Panasonic Corp 積層型半導体装置及び電子機器
JP2010263108A (ja) * 2009-05-08 2010-11-18 Elpida Memory Inc 半導体装置及びその製造方法

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US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
JP3400877B2 (ja) * 1994-12-14 2003-04-28 三菱電機株式会社 半導体装置及びその製造方法
US5855821A (en) * 1995-12-22 1999-01-05 Johnson Matthey, Inc. Materials for semiconductor device assemblies
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
JP2973940B2 (ja) * 1996-09-20 1999-11-08 日本電気株式会社 素子の樹脂封止構造
US6104093A (en) * 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
US6576495B1 (en) * 2000-08-30 2003-06-10 Micron Technology, Inc. Microelectronic assembly with pre-disposed fill material and associated method of manufacture
JP3649169B2 (ja) * 2001-08-08 2005-05-18 松下電器産業株式会社 半導体装置
US6869831B2 (en) * 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
JP4390541B2 (ja) * 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2009049218A (ja) * 2007-08-21 2009-03-05 Nec Electronics Corp 半導体装置及び半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213741A (ja) * 1996-01-31 1997-08-15 Hitachi Chem Co Ltd 半導体装置およびその製造方法
JP2000277564A (ja) * 1999-03-23 2000-10-06 Casio Comput Co Ltd 半導体装置及びその製造方法
JP2005311321A (ja) * 2004-03-22 2005-11-04 Sharp Corp 半導体装置およびその製造方法、並びに、該半導体装置を備えた液晶モジュールおよび半導体モジュール
US20050277231A1 (en) * 2004-06-14 2005-12-15 Hembree David R Underfill and encapsulation of semicondcutor assemblies with materials having differing properties and methods of fabrication using stereolithography
JP2010103129A (ja) * 2008-10-21 2010-05-06 Panasonic Corp 積層型半導体装置及び電子機器
JP2010263108A (ja) * 2009-05-08 2010-11-18 Elpida Memory Inc 半導体装置及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013239660A (ja) * 2012-05-17 2013-11-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US9013031B2 (en) 2013-06-18 2015-04-21 Samsung Electronics Co., Ltd. Semiconductor packages including heat diffusion vias and interconnection vias
KR20160090329A (ko) 2013-11-26 2016-07-29 토레이 엔지니어링 컴퍼니, 리미티드 실장 장치 및 실장 방법

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