JP2011512040A5 - - Google Patents
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- Publication number
- JP2011512040A5 JP2011512040A5 JP2010546411A JP2010546411A JP2011512040A5 JP 2011512040 A5 JP2011512040 A5 JP 2011512040A5 JP 2010546411 A JP2010546411 A JP 2010546411A JP 2010546411 A JP2010546411 A JP 2010546411A JP 2011512040 A5 JP2011512040 A5 JP 2011512040A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- substrate
- oxide
- artificial
- free
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- 239000000758 substrate Substances 0.000 claims 12
- 239000004065 semiconductor Substances 0.000 claims 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000011261 inert gas Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Claims (4)
- 半導体基板の表面を処理するための方法であって、
a)前記半導体基板(1)の前記表面を酸化させ、それにより、自然酸化物(5)を人工酸化物(7)に変換するステップと、
b)前記人工酸化物(7)を除去し、特に、還元性気体プラズマおよび不活性ガスプラズマを備えた還元性プラズマによって、酸化物のない基板表面(11)を得るステップと、
c)特に、接合することによって、前記半導体基板(21)を、前記半導体基板(21)の前記酸化物のない基板表面(25)側を用いて、第2の半導体基板(23)に貼り合わせるステップと、
を備えた方法。 - 前記半導体基板(1)が、Si(110)基板、もしくはSi(100)基板、または、SiGe緩衝層および/またはSiGe緩和層もしくは歪みシリコン層を備えたSi基板である、請求項1に記載の方法。
- ステップa)が、前記人工酸化物(7)が化学量論的なSiO2となるように実行される、請求項1に記載の方法。
- 前記第2の半導体基板(23)が、同様に、ステップa)およびステップb)に基づいて処理されている請求項1に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08290138A EP2091070A1 (en) | 2008-02-13 | 2008-02-13 | Semiconductor substrate surface preparation method |
PCT/IB2009/000141 WO2009101494A1 (en) | 2008-02-13 | 2009-01-23 | Semiconductor substrate surface preparation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011512040A JP2011512040A (ja) | 2011-04-14 |
JP2011512040A5 true JP2011512040A5 (ja) | 2011-09-15 |
Family
ID=39638664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010546411A Withdrawn JP2011512040A (ja) | 2008-02-13 | 2009-01-23 | 半導体基板表面処理方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8062957B2 (ja) |
EP (2) | EP2091070A1 (ja) |
JP (1) | JP2011512040A (ja) |
KR (1) | KR20100114884A (ja) |
CN (1) | CN101952934A (ja) |
WO (1) | WO2009101494A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4894390B2 (ja) * | 2006-07-25 | 2012-03-14 | 信越半導体株式会社 | 半導体基板の製造方法 |
JP6030455B2 (ja) * | 2013-01-16 | 2016-11-24 | 東京エレクトロン株式会社 | シリコン酸化物膜の成膜方法 |
KR102182791B1 (ko) | 2013-09-25 | 2020-11-26 | 에베 그룹 에. 탈너 게엠베하 | 기판 본딩 장치 및 방법 |
JP2015233130A (ja) * | 2014-05-16 | 2015-12-24 | 株式会社半導体エネルギー研究所 | 半導体基板および半導体装置の作製方法 |
US10964664B2 (en) * | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
JP2020057810A (ja) * | 2019-12-23 | 2020-04-09 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | 基板をボンディングする装置および方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5238865A (en) * | 1990-09-21 | 1993-08-24 | Nippon Steel Corporation | Process for producing laminated semiconductor substrate |
DE69331816T2 (de) * | 1992-01-31 | 2002-08-29 | Canon K.K., Tokio/Tokyo | Verfahren zur Herstellung eines Halbleitersubstrats |
JP3116628B2 (ja) * | 1993-01-21 | 2000-12-11 | 株式会社日本自動車部品総合研究所 | 吸着装置 |
JP2978748B2 (ja) * | 1995-11-22 | 1999-11-15 | 日本電気株式会社 | 半導体装置の製造方法 |
US6007641A (en) * | 1997-03-14 | 1999-12-28 | Vlsi Technology, Inc. | Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch |
TW460617B (en) * | 1998-11-06 | 2001-10-21 | United Microelectronics Corp | Method for removing carbon contamination on surface of semiconductor substrate |
US6709989B2 (en) * | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
JP2004266075A (ja) * | 2003-02-28 | 2004-09-24 | Tokyo Electron Ltd | 基板処理方法 |
US6911375B2 (en) * | 2003-06-02 | 2005-06-28 | International Business Machines Corporation | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature |
US7608548B2 (en) | 2003-09-10 | 2009-10-27 | Shin-Etsu Handotai Co., Ltd. | Method for cleaning a multilayer substrate and method for bonding substrates and method for producing a bonded wafer |
-
2008
- 2008-02-13 EP EP08290138A patent/EP2091070A1/en not_active Withdrawn
- 2008-06-10 EP EP08290533A patent/EP2091074A1/en not_active Withdrawn
-
2009
- 2009-01-23 WO PCT/IB2009/000141 patent/WO2009101494A1/en active Application Filing
- 2009-01-23 JP JP2010546411A patent/JP2011512040A/ja not_active Withdrawn
- 2009-01-23 KR KR1020107016195A patent/KR20100114884A/ko not_active Application Discontinuation
- 2009-01-23 US US12/867,217 patent/US8062957B2/en active Active
- 2009-01-23 CN CN2009801050541A patent/CN101952934A/zh active Pending
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