JP2011176279A - 多層集積回路パッケージ - Google Patents

多層集積回路パッケージ Download PDF

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Publication number
JP2011176279A
JP2011176279A JP2010262615A JP2010262615A JP2011176279A JP 2011176279 A JP2011176279 A JP 2011176279A JP 2010262615 A JP2010262615 A JP 2010262615A JP 2010262615 A JP2010262615 A JP 2010262615A JP 2011176279 A JP2011176279 A JP 2011176279A
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JP
Japan
Prior art keywords
package
layer
electrical contacts
package base
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010262615A
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English (en)
Japanese (ja)
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JP2011176279A5 (https=
Inventor
Ronald James Jensen
ロナルド・ジェームズ・ジェンセン
David Scheid
デーヴィッド・シェイド
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Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of JP2011176279A publication Critical patent/JP2011176279A/ja
Publication of JP2011176279A5 publication Critical patent/JP2011176279A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2010262615A 2010-01-27 2010-11-25 多層集積回路パッケージ Pending JP2011176279A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/694,898 2010-01-27
US12/694,898 US8354743B2 (en) 2010-01-27 2010-01-27 Multi-tiered integrated circuit package

Publications (2)

Publication Number Publication Date
JP2011176279A true JP2011176279A (ja) 2011-09-08
JP2011176279A5 JP2011176279A5 (https=) 2014-01-16

Family

ID=43063376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010262615A Pending JP2011176279A (ja) 2010-01-27 2010-11-25 多層集積回路パッケージ

Country Status (3)

Country Link
US (1) US8354743B2 (https=)
EP (1) EP2355150A1 (https=)
JP (1) JP2011176279A (https=)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421237B2 (en) * 2011-07-07 2013-04-16 Cisco Technology, Inc. Stacked memory layers having multiple orientations and through-layer interconnects
KR101849223B1 (ko) * 2012-01-17 2018-04-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102007404B1 (ko) * 2012-12-14 2019-08-05 엘지이노텍 주식회사 발광소자 패키지
CN203015273U (zh) * 2012-12-24 2013-06-19 奥特斯(中国)有限公司 印制电路板
KR20150112985A (ko) * 2013-01-31 2015-10-07 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 멀티-레벨 집적 회로의 회로 선택
TWI489922B (zh) * 2013-07-15 2015-06-21 Mpi Corp Multilayer circuit boards
US9196554B2 (en) * 2013-10-01 2015-11-24 Infineon Technologies Austria Ag Electronic component, arrangement and method
EP3075006A1 (de) 2013-11-27 2016-10-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Leiterplattenstruktur
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
AT515447B1 (de) 2014-02-27 2019-10-15 At & S Austria Tech & Systemtechnik Ag Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
KR102161776B1 (ko) * 2014-03-28 2020-10-06 에스케이하이닉스 주식회사 적층 패키지
TWI592068B (zh) * 2014-10-31 2017-07-11 Mpi Corp Multilayer circuit board
TWI592071B (zh) * 2014-11-14 2017-07-11 Mpi Corp Multilayer circuit board
US9741644B2 (en) 2015-05-04 2017-08-22 Honeywell International Inc. Stacking arrangement for integration of multiple integrated circuits
US9543277B1 (en) 2015-08-20 2017-01-10 Invensas Corporation Wafer level packages with mechanically decoupled fan-in and fan-out areas
WO2017160284A1 (en) * 2016-03-16 2017-09-21 Intel Corporation Stairstep interposers with integrated shielding for electronics packages
FR3050073B1 (fr) * 2016-04-12 2018-05-04 Mbda France Systeme electronique pourvu d'une pluralite de fonctions electroniques interconnectees
CN107564877A (zh) * 2016-06-30 2018-01-09 华邦电子股份有限公司 半导体元件封装体及半导体元件封装制程
CN106206458B (zh) * 2016-07-17 2018-09-25 高燕妮 一种叠层集成电路封装结构
CN109411365A (zh) * 2016-07-17 2019-03-01 高锦 一种防止弯折翘曲的叠层集成电路封装结构的封装方法
CN107889355B (zh) * 2017-11-10 2020-12-01 Oppo广东移动通信有限公司 一种电路板组件以及电子设备
JP6440917B1 (ja) * 2018-04-12 2018-12-19 三菱電機株式会社 半導体装置
MY202999A (en) * 2018-10-17 2024-06-01 Intel Corp Stacked-component placement in multiple-damascene printed wiring boards for semiconductor package substrates
US20210013375A1 (en) * 2019-07-11 2021-01-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN113921506B (zh) * 2021-08-31 2025-11-28 北京时代民芯科技有限公司 一种用于叠层封装的临时悬空结构及制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731166A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Semiconductor device
JP2001015677A (ja) * 1999-06-25 2001-01-19 Toshiba Corp 半導体装置
JP2001085610A (ja) * 1999-09-08 2001-03-30 Meito Chin マルチチップ半導体モジュール及びその製造方法
JP2001144203A (ja) * 1999-11-16 2001-05-25 Mitsubishi Electric Corp キャビティダウン型ｂｇａパッケージ
JP2001217384A (ja) * 2000-02-01 2001-08-10 Sony Corp 積層型半導体装置の製造方法、及び積層型半導体装置
JP2002033443A (ja) * 2000-07-18 2002-01-31 Toshiba Corp 半導体モジュール
JP2004228117A (ja) * 2003-01-20 2004-08-12 Idea System Kk 半導体装置および半導体パッケージ

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437718A (en) * 1981-12-17 1984-03-20 Motorola Inc. Non-hermetically sealed stackable chip carrier package
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
US5235211A (en) * 1990-06-22 1993-08-10 Digital Equipment Corporation Semiconductor package having wraparound metallization
JP2966067B2 (ja) * 1990-09-04 1999-10-25 新光電気工業株式会社 多層リードフレーム
US5155067A (en) * 1991-03-26 1992-10-13 Micron Technology, Inc. Packaging for a semiconductor die
US5490324A (en) * 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
US5497027A (en) * 1993-11-30 1996-03-05 At&T Global Information Solutions Company Multi-chip module packaging system
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
US5608261A (en) * 1994-12-28 1997-03-04 Intel Corporation High performance and high capacitance package with improved thermal dissipation
US5557502A (en) * 1995-03-02 1996-09-17 Intel Corporation Structure of a thermally and electrically enhanced plastic ball grid array package
US5796170A (en) * 1996-02-15 1998-08-18 Northern Telecom Limited Ball grid array (BGA) integrated circuit packages
US5787575A (en) * 1996-09-09 1998-08-04 Intel Corporation Method for plating a bond finger of an intergrated circuit package
US6043559A (en) * 1996-09-09 2000-03-28 Intel Corporation Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US6020629A (en) * 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6603199B1 (en) * 2000-11-28 2003-08-05 National Semiconductor Corporation Integrated circuit package having die with staggered bond pads and die pad assignment methodology for assembly of staggered die in single-tier ebga packages
US20020096767A1 (en) * 2001-01-25 2002-07-25 Cote Kevin J. Cavity down ball grid array package with EMI shielding and reduced thermal resistance
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
US20040194882A1 (en) * 2003-04-07 2004-10-07 Ying-Hao Hung Method for disassembling a stacked-chip package
US7977579B2 (en) * 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731166A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Semiconductor device
JP2001015677A (ja) * 1999-06-25 2001-01-19 Toshiba Corp 半導体装置
JP2001085610A (ja) * 1999-09-08 2001-03-30 Meito Chin マルチチップ半導体モジュール及びその製造方法
JP2001144203A (ja) * 1999-11-16 2001-05-25 Mitsubishi Electric Corp キャビティダウン型ｂｇａパッケージ
JP2001217384A (ja) * 2000-02-01 2001-08-10 Sony Corp 積層型半導体装置の製造方法、及び積層型半導体装置
JP2002033443A (ja) * 2000-07-18 2002-01-31 Toshiba Corp 半導体モジュール
JP2004228117A (ja) * 2003-01-20 2004-08-12 Idea System Kk 半導体装置および半導体パッケージ

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US20110180919A1 (en) 2011-07-28
EP2355150A1 (en) 2011-08-10
US8354743B2 (en) 2013-01-15

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