JP2011122924A5 - - Google Patents

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Publication number
JP2011122924A5
JP2011122924A5 JP2009280469A JP2009280469A JP2011122924A5 JP 2011122924 A5 JP2011122924 A5 JP 2011122924A5 JP 2009280469 A JP2009280469 A JP 2009280469A JP 2009280469 A JP2009280469 A JP 2009280469A JP 2011122924 A5 JP2011122924 A5 JP 2011122924A5
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JP
Japan
Prior art keywords
land
wiring board
contact
pin
semiconductor device
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JP2009280469A
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English (en)
Japanese (ja)
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JP2011122924A (ja
JP5342422B2 (ja
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Priority to JP2009280469A priority Critical patent/JP5342422B2/ja
Priority claimed from JP2009280469A external-priority patent/JP5342422B2/ja
Priority to US12/946,131 priority patent/US8404497B2/en
Publication of JP2011122924A publication Critical patent/JP2011122924A/ja
Publication of JP2011122924A5 publication Critical patent/JP2011122924A5/ja
Application granted granted Critical
Publication of JP5342422B2 publication Critical patent/JP5342422B2/ja
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JP2009280469A 2009-12-10 2009-12-10 半導体装置およびその製造方法 Active JP5342422B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009280469A JP5342422B2 (ja) 2009-12-10 2009-12-10 半導体装置およびその製造方法
US12/946,131 US8404497B2 (en) 2009-12-10 2010-11-15 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009280469A JP5342422B2 (ja) 2009-12-10 2009-12-10 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2011122924A JP2011122924A (ja) 2011-06-23
JP2011122924A5 true JP2011122924A5 (enExample) 2012-10-11
JP5342422B2 JP5342422B2 (ja) 2013-11-13

Family

ID=44141913

Family Applications (1)

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JP2009280469A Active JP5342422B2 (ja) 2009-12-10 2009-12-10 半導体装置およびその製造方法

Country Status (2)

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US (1) US8404497B2 (enExample)
JP (1) JP5342422B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2503594A1 (en) * 2011-03-21 2012-09-26 Dialog Semiconductor GmbH Signal routing optimized IC package ball/pad layout
CN102858096B (zh) * 2012-09-12 2015-04-08 梁锦贤 一种pop封装器件smt预加工装置
KR101474611B1 (ko) * 2012-10-30 2014-12-18 삼성전기주식회사 불량위치 분석 시스템 및 방법
US9362187B2 (en) * 2013-01-18 2016-06-07 Infineon Technologies Ag Chip package having terminal pads of different form factors
US8941224B2 (en) * 2013-03-29 2015-01-27 Kinsus Interconnect Technology Corp. Package structure of a chip and a substrate
US9263409B2 (en) * 2013-05-21 2016-02-16 Esilicon Corporation Mixed-sized pillars that are probeable and routable
KR101535179B1 (ko) * 2014-12-03 2015-07-08 재단법인 서울테크노파크 반도체소자 테스트 소켓용 컨택터 및 그 제조방법
KR20160119942A (ko) * 2015-04-06 2016-10-17 에스케이하이닉스 주식회사 소켓 플러그 접속 구조를 포함하는 반도체 패키지
US20180226271A1 (en) * 2017-01-31 2018-08-09 Skyworks Solutions, Inc. Control of under-fill using a film during fabrication for a dual-sided ball grid array package
JP2018163087A (ja) * 2017-03-27 2018-10-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置の検査装置ならびに半導体装置
JP6848733B2 (ja) * 2017-07-10 2021-03-24 三菱電機株式会社 通電試験用ソケット及び通電試験方法
WO2020036878A1 (en) 2018-08-14 2020-02-20 Rambus Inc. Packaged integrated device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001116795A (ja) * 1999-10-18 2001-04-27 Mitsubishi Electric Corp テスト用ソケット、およびテスト用ソケットに用いる接続シート
JP2001318119A (ja) * 2000-05-02 2001-11-16 Fujitsu Ltd Ｉｃパッケージの接続方法及びｉｃコンタクタ
JP4854148B2 (ja) * 2001-08-28 2012-01-18 富士通セミコンダクター株式会社 半導体装置
JP4601365B2 (ja) 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 半導体装置
JP2008070146A (ja) * 2006-09-12 2008-03-27 Yokowo Co Ltd 検査用ソケット
JP5144170B2 (ja) 2007-08-20 2013-02-13 ルネサスエレクトロニクス株式会社 半導体装置の実装方法
JP5043563B2 (ja) * 2007-08-29 2012-10-10 新光電気工業株式会社 配線基板及びその製造方法
JP2009200101A (ja) * 2008-02-19 2009-09-03 Liquid Design Systems:Kk 半導体チップ及び半導体装置

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