JP2011103607A5 - - Google Patents
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- Publication number
- JP2011103607A5 JP2011103607A5 JP2009258413A JP2009258413A JP2011103607A5 JP 2011103607 A5 JP2011103607 A5 JP 2011103607A5 JP 2009258413 A JP2009258413 A JP 2009258413A JP 2009258413 A JP2009258413 A JP 2009258413A JP 2011103607 A5 JP2011103607 A5 JP 2011103607A5
- Authority
- JP
- Japan
- Prior art keywords
- input
- node
- voltage
- input voltage
- nmos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000903 blocking effect Effects 0.000 claims 9
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009258413A JP5421075B2 (ja) | 2009-11-11 | 2009-11-11 | 入力回路 |
| TW099137779A TW201141065A (en) | 2009-11-11 | 2010-11-03 | Input circuit |
| US12/943,697 US20110109364A1 (en) | 2009-11-11 | 2010-11-10 | Input circuit |
| CN201010553872.2A CN102064694B (zh) | 2009-11-11 | 2010-11-11 | 输入电路 |
| KR1020100112127A KR20110052520A (ko) | 2009-11-11 | 2010-11-11 | 입력 회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009258413A JP5421075B2 (ja) | 2009-11-11 | 2009-11-11 | 入力回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011103607A JP2011103607A (ja) | 2011-05-26 |
| JP2011103607A5 true JP2011103607A5 (enExample) | 2012-10-25 |
| JP5421075B2 JP5421075B2 (ja) | 2014-02-19 |
Family
ID=43973708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009258413A Expired - Fee Related JP5421075B2 (ja) | 2009-11-11 | 2009-11-11 | 入力回路 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20110109364A1 (enExample) |
| JP (1) | JP5421075B2 (enExample) |
| KR (1) | KR20110052520A (enExample) |
| CN (1) | CN102064694B (enExample) |
| TW (1) | TW201141065A (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9152237B1 (en) * | 2014-06-17 | 2015-10-06 | Realtek Semiconductor Corp. | Power bouncing reduction circuit and method thereof |
| JP7063651B2 (ja) * | 2018-02-19 | 2022-05-09 | エイブリック株式会社 | 信号検出回路及び信号検出方法 |
| JP7361474B2 (ja) * | 2019-01-31 | 2023-10-16 | エイブリック株式会社 | 入力回路 |
| JP7548920B2 (ja) | 2019-02-27 | 2024-09-10 | ナノモザイク インコーポレイテッド | ナノセンサーおよびその使用 |
| JP2022083085A (ja) * | 2020-11-24 | 2022-06-03 | 株式会社東芝 | 半導体集積回路 |
| DE102021111796A1 (de) * | 2021-03-19 | 2022-09-22 | Infineon Technologies Ag | Hochgeschwindigkeitsdigitalsignaltreiber mit niedrigem leistungsverbrauch |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877317A (ja) * | 1981-11-02 | 1983-05-10 | Matsushita Electric Ind Co Ltd | シユミツト・トリガ回路 |
| US4539489A (en) * | 1983-06-22 | 1985-09-03 | Motorola, Inc. | CMOS Schmitt trigger circuit |
| US5349246A (en) * | 1992-12-21 | 1994-09-20 | Sgs-Thomson Microelectronics, Inc. | Input buffer with hysteresis characteristics |
| US5386153A (en) * | 1993-09-23 | 1995-01-31 | Cypress Semiconductor Corporation | Buffer with pseudo-ground hysteresis |
| US5459437A (en) * | 1994-05-10 | 1995-10-17 | Integrated Device Technology | Logic gate with controllable hysteresis and high frequency voltage controlled oscillator |
| JPH10229331A (ja) * | 1997-02-14 | 1998-08-25 | Texas Instr Japan Ltd | 入力回路 |
| JPH10290145A (ja) * | 1997-04-14 | 1998-10-27 | Texas Instr Japan Ltd | ヒステリシス回路 |
| KR100266011B1 (ko) * | 1997-10-01 | 2000-09-15 | 김영환 | 히스테리시스입력버퍼 |
| US6433602B1 (en) * | 2000-08-30 | 2002-08-13 | Lattice Semiconductor Corp. | High speed Schmitt Trigger with low supply voltage |
| JP2004096319A (ja) * | 2002-08-30 | 2004-03-25 | Mitsubishi Electric Corp | シュミットトリガ回路 |
| US7183826B2 (en) * | 2004-03-11 | 2007-02-27 | Seiko Epson Corporation | High hysteresis width input circuit |
| WO2007093956A1 (en) * | 2006-02-16 | 2007-08-23 | Nxp B.V. | Transformation of an input signal into a logical output voltage level with a hysteresis behavior |
| JP4887111B2 (ja) * | 2006-10-12 | 2012-02-29 | オンセミコンダクター・トレーディング・リミテッド | シュミット回路 |
| JP4983562B2 (ja) * | 2007-11-16 | 2012-07-25 | 富士通セミコンダクター株式会社 | シュミット回路 |
-
2009
- 2009-11-11 JP JP2009258413A patent/JP5421075B2/ja not_active Expired - Fee Related
-
2010
- 2010-11-03 TW TW099137779A patent/TW201141065A/zh unknown
- 2010-11-10 US US12/943,697 patent/US20110109364A1/en not_active Abandoned
- 2010-11-11 CN CN201010553872.2A patent/CN102064694B/zh not_active Expired - Fee Related
- 2010-11-11 KR KR1020100112127A patent/KR20110052520A/ko not_active Ceased
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