CN102064694B - 输入电路 - Google Patents

输入电路 Download PDF

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Publication number
CN102064694B
CN102064694B CN201010553872.2A CN201010553872A CN102064694B CN 102064694 B CN102064694 B CN 102064694B CN 201010553872 A CN201010553872 A CN 201010553872A CN 102064694 B CN102064694 B CN 102064694B
Authority
CN
China
Prior art keywords
node
voltage
circuit
nmos pass
pmos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010553872.2A
Other languages
English (en)
Chinese (zh)
Other versions
CN102064694A (zh
Inventor
山崎太郎
宇都宫文靖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN102064694A publication Critical patent/CN102064694A/zh
Application granted granted Critical
Publication of CN102064694B publication Critical patent/CN102064694B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
CN201010553872.2A 2009-11-11 2010-11-11 输入电路 Expired - Fee Related CN102064694B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-258413 2009-11-11
JP2009258413A JP5421075B2 (ja) 2009-11-11 2009-11-11 入力回路

Publications (2)

Publication Number Publication Date
CN102064694A CN102064694A (zh) 2011-05-18
CN102064694B true CN102064694B (zh) 2015-06-10

Family

ID=43973708

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010553872.2A Expired - Fee Related CN102064694B (zh) 2009-11-11 2010-11-11 输入电路

Country Status (5)

Country Link
US (1) US20110109364A1 (enExample)
JP (1) JP5421075B2 (enExample)
KR (1) KR20110052520A (enExample)
CN (1) CN102064694B (enExample)
TW (1) TW201141065A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9152237B1 (en) * 2014-06-17 2015-10-06 Realtek Semiconductor Corp. Power bouncing reduction circuit and method thereof
JP7063651B2 (ja) * 2018-02-19 2022-05-09 エイブリック株式会社 信号検出回路及び信号検出方法
JP7361474B2 (ja) * 2019-01-31 2023-10-16 エイブリック株式会社 入力回路
JP7548920B2 (ja) 2019-02-27 2024-09-10 ナノモザイク インコーポレイテッド ナノセンサーおよびその使用
JP2022083085A (ja) * 2020-11-24 2022-06-03 株式会社東芝 半導体集積回路
DE102021111796A1 (de) * 2021-03-19 2022-09-22 Infineon Technologies Ag Hochgeschwindigkeitsdigitalsignaltreiber mit niedrigem leistungsverbrauch

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539489A (en) * 1983-06-22 1985-09-03 Motorola, Inc. CMOS Schmitt trigger circuit
US5386153A (en) * 1993-09-23 1995-01-31 Cypress Semiconductor Corporation Buffer with pseudo-ground hysteresis
US5594361A (en) * 1994-05-10 1997-01-14 Integrated Device Technology, Inc. Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
CN101385243A (zh) * 2006-02-16 2009-03-11 Nxp股份有限公司 利用迟滞行为将输入信号转换为逻辑输出电压电平

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5877317A (ja) * 1981-11-02 1983-05-10 Matsushita Electric Ind Co Ltd シユミツト・トリガ回路
US5349246A (en) * 1992-12-21 1994-09-20 Sgs-Thomson Microelectronics, Inc. Input buffer with hysteresis characteristics
JPH10229331A (ja) * 1997-02-14 1998-08-25 Texas Instr Japan Ltd 入力回路
JPH10290145A (ja) * 1997-04-14 1998-10-27 Texas Instr Japan Ltd ヒステリシス回路
KR100266011B1 (ko) * 1997-10-01 2000-09-15 김영환 히스테리시스입력버퍼
US6433602B1 (en) * 2000-08-30 2002-08-13 Lattice Semiconductor Corp. High speed Schmitt Trigger with low supply voltage
JP2004096319A (ja) * 2002-08-30 2004-03-25 Mitsubishi Electric Corp シュミットトリガ回路
US7183826B2 (en) * 2004-03-11 2007-02-27 Seiko Epson Corporation High hysteresis width input circuit
JP4887111B2 (ja) * 2006-10-12 2012-02-29 オンセミコンダクター・トレーディング・リミテッド シュミット回路
JP4983562B2 (ja) * 2007-11-16 2012-07-25 富士通セミコンダクター株式会社 シュミット回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539489A (en) * 1983-06-22 1985-09-03 Motorola, Inc. CMOS Schmitt trigger circuit
US5386153A (en) * 1993-09-23 1995-01-31 Cypress Semiconductor Corporation Buffer with pseudo-ground hysteresis
US5594361A (en) * 1994-05-10 1997-01-14 Integrated Device Technology, Inc. Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
CN101385243A (zh) * 2006-02-16 2009-03-11 Nxp股份有限公司 利用迟滞行为将输入信号转换为逻辑输出电压电平

Also Published As

Publication number Publication date
JP2011103607A (ja) 2011-05-26
CN102064694A (zh) 2011-05-18
JP5421075B2 (ja) 2014-02-19
KR20110052520A (ko) 2011-05-18
US20110109364A1 (en) 2011-05-12
TW201141065A (en) 2011-11-16

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Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160315

Address after: Chiba County, Japan

Patentee after: SEIKO INSTR INC

Address before: Chiba, Chiba, Japan

Patentee before: Seiko Instruments Inc.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: EPPs Lingke Co. Ltd.

Address before: Chiba County, Japan

Patentee before: SEIKO INSTR INC

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150610

Termination date: 20201111