CN102064694B - Input circuit - Google Patents
Input circuit Download PDFInfo
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- CN102064694B CN102064694B CN201010553872.2A CN201010553872A CN102064694B CN 102064694 B CN102064694 B CN 102064694B CN 201010553872 A CN201010553872 A CN 201010553872A CN 102064694 B CN102064694 B CN 102064694B
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- pmos transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
- H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
Abstract
Provided is an input circuit having hysteresis characteristics that is capable of operating in a wide range of power supply voltage conditions while suppressing power supply voltage dependence of a hysteresis voltage and a response speed. The input circuit is provided with: a circuit for obtaining a small hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 to 103) and an inverter (501)); and a circuit for obtaining a large hysteresis voltage under the condition of low power supply voltage (formed of PMOS transistors (101 and 104) and the inverter (501)).
Description
Technical field
The present invention relates to the input circuit in semiconductor integrated circuit, more specifically relate to the improvement of the supply voltage characteristic of the input circuit of band magnetic hysteresis (hysteresis) characteristic.
Background technology
Traditional input circuit (with reference to patent documentation 1) with hysteresis characteristic is described.
Figure 14 is the circuit diagram of the input circuit representing traditional band hysteresis characteristic.When the input voltage VIN of input terminal 401 is transitioned into low level from high level, the PMOS transistor 803 of magnetic hysteresis generation is ended.Thus, the threshold voltage of inverter circuit is determined by the ratio of the conducting resistance of PMOS transistor 801 and nmos pass transistor 901.When input voltage VIN is transitioned into high level from low level, PMOS transistor 803 conducting of magnetic hysteresis generation.Therefore, the conducting resistance of PMOS transistor 801 side correspondingly diminishes than nmos pass transistor 901 side.Thus, the threshold voltage of inverter circuit is determined by the ratio of the conducting resistance of 2 PMOS transistor 801 and 803 and nmos pass transistor 901.Thus, the threshold value of inverter circuit is when input voltage VIN is transitioned into high level from low level, and input voltage VIN is than rising when being transitioned into low level from high level.That is, the threshold value of inverter circuit has hysteresis characteristic.
In addition, Figure 15 is the circuit diagram of other example of the input circuit representing conventional belt hysteresis characteristic.When input voltage VIN is transitioned into high level from low level, PMOS transistor 804 with become conducting state and link, the PMOS transistor 805 of switch becomes cut-off state, therefore compared with the circuit of Figure 14, can reduce current sinking during switch.
Patent documentation 1: Japanese Unexamined Patent Publication 10-229331 publication
But in the conventional technology, as described below, supply voltage correlation is embodied in hysteresis voltage or response speed.
First, the input circuit of the band hysteresis characteristic of Figure 15 is described.When making input voltage VIN be transitioned into high level from low level under low supply voltage condition, input voltage VIN is from the threshold voltage of low level close to circuit.Between the gate/source of then PMOS transistor 801 and 804, voltage is less than transistor threshold.At this moment, owing to entering weak anti-phase region, so conducting resistance can increase than during high power supply voltage.Therefore, under low supply voltage condition, hysteresis voltage can diminish.In addition, in order to increase hysteresis voltage during low supply voltage, increase the ratio of conducting resistance relative to the conducting resistance of PMOS transistor 801 side of nmos pass transistor 901 side, when supply voltage is higher, the threshold value of circuit will raise like this, and can not accept the less input signal of the amplitude of oscillation.Further, along with the increase of the conducting resistance of nmos pass transistor 901, response speed at low supply voltages also can decline.
Then, the input circuit of the band hysteresis characteristic of Figure 14 is described.When making input voltage VIN be transitioned into high level from low level under low supply voltage condition, between the gate/source of PMOS transistor 801, voltage is less than threshold value and enters weak anti-phase region.Like this, conducting resistance can than becoming large during high power supply voltage.But before the lead-out terminal 402 of circuit is reversed to high level, between the gate/source of PMOS transistor 803, voltage is equal with supply voltage.Therefore, the conducting resistance of the PMOS transistor 803 when input voltage VIN is transitioned into high level from low level, when supply voltage is more than transistor threshold, almost uncorrelated with supply voltage.Further, under low supply voltage condition, can see that the impact of the current driving ability of PMOS transistor 803 is comparatively large, therefore the conducting resistance of PMOS transistor side diminishes.Like this, under low supply voltage condition, hysteresis voltage becomes large.As mentioned above, when the threshold value of circuit raises, the input signal that the amplitude of oscillation is less can not be accepted.Further, can not be too high if be designed to circuit threshold value under low supply voltage condition, then PMOS transistor 801 is at the Near Threshold of circuit, and under the such supply voltage condition of strong anti-phase region action, hysteresis voltage can diminish.In addition, under low supply voltage condition, the current driving ability of nmos pass transistor 901 pair pmos transistor side is less, and the response speed therefore under low supply voltage condition can decline.
Summary of the invention
The present invention forms in view of the design of above-mentioned problem, provide buffering hysteresis voltage or response speed supply voltage correlation and under the supply voltage condition of wide region the input circuit of the band hysteresis characteristic of action.
In order to solve the problem of conventional art, the input circuit of band hysteresis characteristic of the present invention is formed as follows.
A kind of input circuit, is characterized in that comprising: the input terminal of input voltage VIN input; Export the lead-out terminal based on the output signal of input voltage VIN; When input voltage VIN is low level to the first PMOS transistor that first node charges; The first nmos pass transistor first node being discharged when input voltage VIN is high level; When input voltage VIN is low level to the second PMOS transistor that first node charges; Block the second PMOS transistor when the voltage of first node is low level and block unit to first of the charge path of first node; And when the voltage of first node is high level to the 3rd PMOS transistor that first node charges.
In addition, a kind of input circuit, is characterized in that comprising: the input terminal of input voltage VIN input; Export the lead-out terminal based on the output signal of input voltage VIN; When input voltage VIN is low level to the first PMOS transistor that first node charges; The first nmos pass transistor first node being discharged when input voltage VIN is high level; The second nmos pass transistor first node being discharged when input voltage VIN is high level; Block the discharge path from first node of the second nmos pass transistor when the voltage of first node is high level second blocks unit; And the 3rd nmos pass transistor first node being discharged when the voltage of first node is low level.
In the present invention, larger hysteresis voltage can be guaranteed under wide supply voltage condition without the need to using logical circuit or operational amplification circuit etc.In addition, due to the conducting resistance of nmos pass transistor side can be made to be less than conventional art relative to the ratio of the conducting resistance of PMOS transistor side, so can prevent the response speed in low supply voltage action from declining compared with conventional art.And, due to the supply voltage correlation hysteresis characteristic less than traditional circuit can be obtained, so can not design to increasing circuit scale.
To sum up, circuit of the present invention has compared with conventional art, can not increasing circuit scale and cushion the effect of the supply voltage correlation of hysteresis voltage or response speed.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the input circuit representing present embodiment.
Fig. 2 is the circuit diagram of the input circuit representing the second execution mode.
Fig. 3 is the circuit diagram of the input circuit representing the 3rd execution mode.
Fig. 4 is the circuit diagram of the input circuit representing the 4th execution mode.
Fig. 5 is the circuit diagram of the input circuit representing the 5th execution mode.
Fig. 6 is the circuit diagram of the input circuit representing the 6th execution mode.
Fig. 7 is the circuit diagram of the input circuit representing the 7th execution mode.
Fig. 8 is the circuit diagram of the input circuit representing the 8th execution mode.
Fig. 9 is the circuit diagram of the first case of the input circuit representing the 9th execution mode.
Figure 10 is the circuit diagram of the second case of the input circuit representing the 9th execution mode.
Figure 11 is the circuit diagram of the 3rd example of the input circuit representing the 9th execution mode.
Figure 12 is the circuit diagram of the 4th example of the input circuit representing the 9th execution mode.
Figure 13 is the circuit diagram of the input circuit representing the tenth execution mode.
Figure 14 is the circuit diagram of the first case representing traditional input circuit.
Figure 15 is the circuit diagram of the second case representing traditional input circuit.
Embodiment
Below, with reference to accompanying drawing, embodiments of the present invention are described.
First execution mode
Fig. 1 is the input circuit with hysteresis characteristic of present embodiment.
The input circuit with hysteresis characteristic of present embodiment, comprising: PMOS transistor 101 ~ 104; Nmos pass transistor 201; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.
The source electrode of PMOS transistor 101,102 and 104 is connected with VDD, and the source electrode of nmos pass transistor 201 is connected with VSS.The grid of PMOS transistor 101 and nmos pass transistor 201 is all connected with input terminal 401, and drain electrode is all connected with node N1.The input of inverter 501 is connected with node N1, and output is connected with lead-out terminal 402.The grid of PMOS transistor 102 is connected with input terminal 401, and drain electrode is connected with node N2.The grid of PMOS transistor 103 is connected with lead-out terminal 402, and source electrode is connected with node N2, and drain electrode is connected with node N1.PMOS transistor 103 is located between node N1 and node N2 as blocking unit.The grid of PMOS transistor 104 is connected with lead-out terminal 402, and drain electrode is connected with node N1.PMOS transistor 101 and nmos pass transistor 201 form inverter circuit.
In addition, although not illustrated, the back grid of PMOS transistor 101 ~ 104 is connected with VDD or the current potential higher than source potential, and the back grid of nmos pass transistor 201 is connected with VSS or the current potential lower than source potential.
Then, the action with the input circuit of hysteresis characteristic of present embodiment is described.
When the input voltage VIN of input terminal 401 is transitioned into low level from high level, the voltage of lead-out terminal 402 was high level be less than the threshold value of whole circuit in input voltage VIN before.Therefore, PMOS transistor 103 and 104 is in cut-off state.Then, when input voltage VIN is less than the threshold value of the circuit be made up of PMOS transistor 101 and nmos pass transistor 201, node N1 is transitioned into high level, and lead-out terminal 402 is transitioned into low level from high level.That is, the threshold value of whole circuit is determined by the threshold value of circuit be made up of PMOS transistor 101 and nmos pass transistor 201, and this value is determined by the ratio of the conducting resistance of PMOS transistor 101 and nmos pass transistor 201.
When input voltage VIN is transitioned into high level from low level, the voltage of lead-out terminal 402 was low level exceed the threshold value of whole circuit in input voltage VIN before, and PMOS transistor 103 and 104 is in conducting state.Therefore, compared with when being transitioned into low level with input from high level, the conducting resistance of PMOS transistor 101 side only reduces the amount being equivalent to PMOS transistor 102 and 104.Like this, the threshold value of whole circuit rises, and input circuit has hysteresis characteristic.
At this, from the circuit diagram of Fig. 1 except PMOS transistor 104, and the structure be made up of PMOS transistor 101 ~ 103, nmos pass transistor 201, inverter 501 is utilized to consider supply voltage correlation.At low supply voltages input voltage VIN from low level close to threshold voltage time, PMOS transistor 101 and 102 enters weak anti-phase region.The conducting resistance of PMOS transistor 101 and 102 at this moment, namely can become large than input voltage VIN near threshold voltage when the high power supply voltage of strong anti-phase region action.Therefore, under low supply voltage condition, hysteresis voltage diminishes.
Then, from the circuit diagram of Fig. 1 except PMOS transistor 102 and 103, and the structure be made up of PMOS transistor 101 and 104, nmos pass transistor 201, inverter 501 is utilized to consider supply voltage correlation.As mentioned above, under low supply voltage condition, when input voltage VIN is from the threshold voltage of low level close to circuit, PMOS transistor 101 and 104 enters weak anti-phase region, and conducting resistance can than also large under high power supply voltage condition.At this, between the gate/source of PMOS transistor 104, voltage is equal with supply voltage before lead-out terminal 402 is reversed to high level.Therefore, when supply voltage is more than the transistor threshold of PMOS transistor 104, the conducting resistance of PMOS transistor 104 is relevant to supply voltage hardly.In addition, supply voltage is less, and the impact of the current driving ability of PMOS transistor 104 is larger, and the conducting resistance of PMOS transistor side diminishes.Therefore, under low supply voltage condition, hysteresis voltage becomes large.
The input circuit of present embodiment, by arranging 2 circuit, can guarantee that under low supply voltage condition the hysteresis voltage of the circuit working making PMOS transistor 101,104 and inverter 501 is comparatively large, and under high power supply voltage condition, also can guarantee to make the hysteresis voltage of the circuit working of PMOS transistor 101 ~ 103 and inverter 501 larger.So, the supply voltage correlation of hysteresis voltage can be cushioned.Therefore, when high power supply voltage without the need to increasing the current driving ability of PMOS transistor 102, and the current driving ability of PMOS transistor 102 can be reduced.In addition, current sinking during switch can also be reduced.And owing to can reduce the ratio of PMOS transistor 102 relative to the current driving ability of nmos pass transistor 201, when low supply voltage, the response speed from input low level to high level can not reduce.
As described above, according to the input circuit with hysteresis characteristic of the first execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, current sinking during switch can be reduced without the need to increasing circuit scale.
Second execution mode
Fig. 2 is the input circuit with hysteresis characteristic of the second execution mode.
The input circuit with hysteresis characteristic of the second execution mode, comprising: PMOS transistor 101 ~ 104; Nmos pass transistor 201; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.Second execution mode is different from the first execution mode in the following areas.The drain electrode of PMOS transistor 102 is connected with node N1, and source electrode is connected with node N2, and the drain electrode blocking unit and PMOS transistor 103 is connected with node N2, and source electrode VDD connects.
Then the input circuit with hysteresis characteristic of the second execution mode is described.
Compared with the first execution mode, the structure of the second execution mode is for having changed PMOS transistor 102 and PMOS transistor 103.In this case, carry out the action same with the first execution mode, and same effect can be obtained.
Thus, according to the input circuit with hysteresis characteristic of the second execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, current sinking during switch can be reduced without the need to increasing circuit scale.
3rd execution mode
Fig. 3 is the input circuit with hysteresis characteristic of the 3rd execution mode.
The input circuit with hysteresis characteristic of the 3rd execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.
The source electrode of nmos pass transistor 201,202 and 204 is connected with VSS, and the source electrode of PMOS transistor 101 is connected with VDD.The grid of PMOS transistor 101 and nmos pass transistor 201 is all connected with input terminal 401, and drain electrode is all connected with node N1.The input of inverter 501 is connected with node N1, and output is connected with lead-out terminal 402.The grid of nmos pass transistor 202 is connected with input terminal 401, and drain electrode is connected with node N3.The grid of nmos pass transistor 203 is connected with lead-out terminal 402, and source electrode is connected with node N3, and drain electrode is connected with node N1.Nmos pass transistor 203 is located between node N1 and node N3 as blocking unit.The grid of nmos pass transistor 204 is connected with lead-out terminal 402, and drain electrode is connected with node N1.
In addition, although not illustrated, the back grid of nmos pass transistor 201 ~ 204 is connected with VSS or the current potential lower than source potential, and the back grid of PMOS transistor 101 is connected with VDD or the current potential higher than source potential.
Then the input circuit with hysteresis characteristic of the 3rd execution mode is described.
When input voltage VIN is transitioned into high level from low level, the voltage of lead-out terminal 402 was low level be less than the threshold value of whole circuit in input voltage VIN before.Therefore, nmos pass transistor 203 and 204 becomes cut-off state.Then, when input voltage VIN exceedes the threshold value of the circuit be made up of PMOS transistor 101 and nmos pass transistor 201, node N1 is transitioned into low level, and lead-out terminal 402 is transitioned into high level from low level.That is, the threshold value of whole circuit utilizes the threshold value of the circuit be made up of PMOS transistor 101 and nmos pass transistor 201 to determine, this value is determined by the ratio of the conducting resistance of PMOS transistor 101 and nmos pass transistor 201.
When input voltage VIN is transitioned into low level from high level, the voltage of lead-out terminal 402 was high level be less than the threshold value of whole circuit in input voltage VIN before.Therefore, nmos pass transistor 203 and 204 becomes conducting state.Therefore, compared with when being transitioned into high level with input from low level, the conducting resistance of nmos pass transistor 201 side only reduces the amount being equivalent to nmos pass transistor 202 and 204.Like this, the threshold value of whole circuit rises, and input circuit has hysteresis characteristic.
At this, from the circuit diagram of Fig. 3 except nmos pass transistor 204, the structure be made up of nmos pass transistor 201 ~ 203, PMOS transistor 101, inverter 501 is utilized to consider supply voltage correlation.At low supply voltages input voltage VIN from high level close to threshold voltage time, nmos pass transistor 201 and 202 enters weak anti-phase region.The conducting resistance of nmos pass transistor 201 and 202 at this moment can than input voltage VIN near threshold voltage namely in strong anti-phase region action time large.Therefore, under low supply voltage condition, hysteresis voltage diminishes.
Then, from the circuit diagram of Fig. 3 except nmos pass transistor 202 and 203, and the structure be made up of nmos pass transistor 201 and 204, PMOS transistor 101, inverter 501 is utilized to consider supply voltage correlation.As mentioned above, nmos pass transistor 201 and 204, under low supply voltage condition, when input voltage VIN is from the threshold voltage of high level close to circuit, enters weak anti-phase region, and conducting resistance can than also large under high power supply voltage condition.At this, between the gate/source of nmos pass transistor 204, voltage is equal with supply voltage before lead-out terminal 402 is reversed to low level.Therefore, when supply voltage is more than the transistor threshold of nmos pass transistor 204, the conducting resistance of nmos pass transistor 204 is almost uncorrelated with supply voltage.In addition, supply voltage is less, and the impact of the current driving ability of nmos pass transistor 204 is larger, and the conducting resistance of nmos pass transistor side can be less.Therefore, under low supply voltage condition, hysteresis voltage becomes large.
The input circuit of present embodiment, by arranging 2 circuit, can guarantee that under low supply voltage condition the hysteresis voltage of the circuit working making nmos pass transistor 201,204 and inverter 501 is comparatively large, and it is larger to guarantee to make the hysteresis voltage of the circuit working of nmos pass transistor 201 ~ 203 and inverter 501 under high power supply voltage condition.Like this, the supply voltage correlation of hysteresis voltage can be cushioned.Therefore, when high power supply voltage without the need to increasing the current driving ability of nmos pass transistor 202, and the current driving ability of nmos pass transistor 202 can be reduced.Therefore, it is possible to current sinking when reducing switch.And can make smaller relative to the current driving ability of PMOS transistor 101 of nmos pass transistor 202, therefore when low supply voltage, the response speed from input low level to high level can not decline.
As described above, according to the input circuit with hysteresis characteristic of the 3rd execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch.
4th execution mode
Fig. 4 is the input circuit with hysteresis characteristic of the 4th execution mode.
The input circuit with hysteresis characteristic of the 4th execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.4th execution mode is different from the 3rd execution mode in the following areas.The drain electrode of nmos pass transistor 202 is connected with node N1, and source electrode is connected with node N3, and the drain electrode blocking unit and nmos pass transistor 203 is connected with node N3, and source electrode is connected with VSS.
Then the input circuit with hysteresis characteristic of the 4th execution mode is described.
Compared with the 3rd execution mode, the structure of the 4th execution mode is for having changed nmos pass transistor 202 and nmos pass transistor 203.In this case, carry out the action same with the 3rd execution mode, and same effect can be obtained.
Thus, according to the input circuit with hysteresis characteristic of the 4th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, current sinking during switch can be reduced without the need to increasing circuit scale.
5th execution mode
Fig. 5 is the input circuit with hysteresis characteristic of the 5th execution mode.
The input circuit with hysteresis characteristic of the 5th execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101 ~ 104; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.
The source electrode of nmos pass transistor 201,202 and 204 is connected with VSS, and the source electrode of PMOS transistor 101,102 and 104 is connected with VDD.The grid of PMOS transistor 101 and nmos pass transistor 201 is all connected with input terminal 401, and drain electrode is all connected with node N1.The input of inverter 501 is connected with node N1, and output is connected with lead-out terminal 402.The grid of nmos pass transistor 202 is connected with input terminal 401, and drain electrode is connected with node N3.The grid of nmos pass transistor 203 is connected with lead-out terminal 402, and source electrode is connected with node N3, and drain electrode is connected with node N1.The grid of nmos pass transistor 204 is connected with lead-out terminal 402, and drain electrode is connected with node N1.The grid of PMOS transistor 102 is connected with input terminal 401, and drain electrode is connected with node N2.The grid of PMOS transistor 103 is connected with lead-out terminal 402, and source electrode is connected with node N2, and drain electrode is connected with node N1.The grid of PMOS transistor 104 is connected with lead-out terminal 402, and drain electrode is connected with node N1.
In addition, although not illustrated, the back grid of nmos pass transistor 201 ~ 204 is connected with VSS or the current potential lower than source potential, and the back grid of PMOS transistor 101 ~ 104 is connected with VDD or the current potential higher than source potential.
Then the input circuit with hysteresis characteristic of the 5th execution mode is described.
The input circuit with hysteresis characteristic of the 5th execution mode, for merging the circuit structure of the first execution mode and the 3rd execution mode.Thus, the structure (PMOS transistor 101 ~ 103, nmos pass transistor 201 ~ 203 and inverter 501) that hysteresis voltage diminishes when low supply voltage and when low supply voltage hysteresis voltage become large structure (PMOS transistor 101,104, nmos pass transistor 201,204 and inverter 501) and have 2 separately.
The input circuit of present embodiment, by arranging 2 circuit, can guarantee to make under low supply voltage condition PMOS transistor 101,104, the hysteresis voltage of the circuit working of nmos pass transistor 201,204 and inverter 501 is comparatively large, and under high power supply voltage condition, also can guarantee to make the hysteresis voltage of the circuit working of PMOS transistor 101 ~ 103, nmos pass transistor 201 ~ 203 and inverter 501 larger.Like this, the supply voltage correlation of hysteresis voltage can be cushioned.Therefore, when high power supply voltage without the need to increasing the current driving ability of nmos pass transistor 202, PMOS transistor 102, and the current driving ability of PMOS transistor 102 and nmos pass transistor 202 can be reduced.In addition, current sinking during switch can also be reduced.And, nmos pass transistor 202 can be reduced further relative to the ratio of the current driving ability of PMOS transistor 101 and PMOS transistor 102 ratio relative to the current driving ability of nmos pass transistor 201, therefore, when low supply voltage, the response speed from input low level to high level can not reduce.In addition, by adopting such structure, larger hysteresis voltage can be got.
As previously discussed, according to the input circuit with hysteresis characteristic of the 5th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch, and larger hysteresis voltage can be obtained.
6th execution mode
Fig. 6 is the input circuit with hysteresis characteristic of the 6th execution mode.
The input circuit with hysteresis characteristic of the 6th execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101 ~ 104; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.6th execution mode is different from the 5th execution mode in the following areas.The drain electrode of nmos pass transistor 202 is connected with node N1, and source electrode is connected with node N3, and the drain electrode of nmos pass transistor 203 is connected with node N3, and source electrode is connected with VSS.
Then the input circuit with hysteresis characteristic of the 6th execution mode is described.
Compared with the 5th execution mode, the structure of the 6th execution mode is for having changed nmos pass transistor 202 and nmos pass transistor 203.In this case, the action same with the 5th execution mode can be carried out, and same effect can be obtained.
Above, according to the input circuit with hysteresis characteristic of the 6th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch, and larger hysteresis voltage can be obtained.
7th execution mode
Fig. 7 is the input circuit with hysteresis characteristic of the 7th execution mode.
The input circuit with hysteresis characteristic of the 7th execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101 ~ 104; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.7th execution mode is different from the 5th execution mode in the following areas.The drain electrode of PMOS transistor 102 is connected with node N1, and source electrode is connected with node N2, and the drain electrode of PMOS transistor 103 is connected with node N2, and source electrode is connected with VDD.
Then the input circuit with hysteresis characteristic of the 7th execution mode is described.
Compared with the 5th execution mode, the structure of the 7th execution mode is for having changed PMOS transistor 102 and PMOS transistor 103.In this case, the action same with the 5th execution mode can be carried out, and same effect can be obtained.
Above, according to the input circuit with hysteresis characteristic of the 7th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch, and larger hysteresis voltage can be obtained.
8th execution mode
Fig. 8 is the input circuit with hysteresis characteristic of the 8th execution mode.
The input circuit with hysteresis characteristic of the 8th execution mode, comprising: nmos pass transistor 201 ~ 204; PMOS transistor 101 ~ 104; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.8th execution mode is different from the 5th execution mode in the following areas.The drain electrode of PMOS transistor 102 is connected with node N1, and source electrode is connected with node N2, the drain electrode of PMOS transistor 103 is connected with node N2, and source electrode is connected with VDD, the drain electrode of nmos pass transistor 202 is connected with node N1, and source electrode is connected with N3, the drain electrode of nmos pass transistor 203 is connected with node N3, and source electrode is connected with VSS.
Then the input circuit with hysteresis characteristic of the 8th execution mode is described.
Compared with the 5th execution mode, the structure of the 8th execution mode is for having changed PMOS transistor 102 and PMOS transistor 103, nmos pass transistor 202 and nmos pass transistor 203.In this case, the action same with the 5th execution mode can be carried out, and same effect can be obtained.
Above, according to the input circuit with hysteresis characteristic of the 8th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch, and larger hysteresis voltage can be obtained.
9th execution mode
Fig. 9 is the input circuit with hysteresis characteristic of the 9th execution mode.
The input circuit with hysteresis characteristic of the 9th execution mode, comprising: PMOS transistor 101 ~ 104; Nmos pass transistor 201; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; Lead-out terminal 402; And switch element 601,701.Compared with the first execution mode, its difference is to have added switch element 601 between PMOS transistor 101 and VDD, and has added switch element 701 between node N1 and VSS.
Then the input circuit with hysteresis characteristic of the 9th execution mode is described.
9th execution mode is configured on the circuit of the first execution mode, added switch element 601,701.By such formation, utilize the enable signal inputing to switch element to be controlled to and electrically disconnect when allowing (enable), and be electrically connected when forbidding (disable).The action of switch element to other does not have an impact.Therefore, do not change with the first execution mode, and the effect equal with the first execution mode can be obtained.In addition, although not illustrated, this switch element is used for the second to the 8th execution mode and also plays same effect.
Figure 10 to Figure 12 is the circuit diagram of other example of the present embodiment at the insertion position representing alternation switch element 602,603,604,702.So, even if the insertion position of alternation switch element, also there is same effect.In addition, although not illustrated, this switch element is used for the second to the 8th execution mode and also plays same effect.
Above, according to the input circuit with hysteresis characteristic of the 9th execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.In addition, without the need to increasing circuit scale, and current sinking when can reduce switch, and larger hysteresis voltage can be obtained.
Tenth execution mode
Figure 13 is the input circuit with hysteresis characteristic of the tenth execution mode.
The input circuit with hysteresis characteristic of the tenth execution mode, comprising: PMOS transistor 101 ~ 104; Nmos pass transistor 201; Inverter 501; First power supply 301 (following VDD); The second source 302 (following VSS) that voltage ratio first power supply is low; Input terminal 401; And lead-out terminal 402.Tenth execution mode is different from the first execution mode in the following areas.Change the position connecting inverter 501, and lead-out terminal 402 is connected with node N1, and make the logic inversion of lead-out terminal 402.
Then the input circuit with hysteresis characteristic of the tenth execution mode is described.
Compared with the first execution mode, the structure of the tenth execution mode is that lead-out terminal 402 is connected with node N1.Therefore, only change the logic of lead-out terminal 402, and other action is not had an impact.Thus, even the input circuit of the output logic anti-phase with the first execution mode, also the effect same with the first execution mode can be obtained.In addition, although not illustrated, same effect is also played for the second to the 9th execution mode.
Above, according to the input circuit with hysteresis characteristic of the tenth execution mode, the supply voltage correlation of hysteresis voltage or response speed can be cushioned, and action can be carried out under the supply voltage condition of wide region.
Description of reference numerals
301 first power supplys (VDD)
302 second sources (VSS)
401 input terminals
402 lead-out terminals
501 inverter circuits
601 ~ 604,701 ~ 702 switch elements
Claims (9)
1. an input circuit, is characterized in that comprising:
The input terminal that input voltage is transfused to;
Export the lead-out terminal based on the output signal of described input voltage;
Grid is transfused to described input voltage and when described input voltage is low level to the first PMOS transistor that first node charges;
Grid be transfused to described input voltage and make the first nmos pass transistor that described first node discharges when described input voltage is high level;
Grid is transfused to described input voltage and when described input voltage is low level to the second PMOS transistor that described first node charges;
Block described second PMOS transistor when the voltage of described first node is low level and block unit to first of the charge path of described first node; And
When the voltage of described first node is high level to the 3rd PMOS transistor that described first node charges.
2. input circuit as claimed in claim 1, is characterized in that:
Described first blocks unit is made up of PMOS transistor.
3. input circuit as claimed in claim 1 or 2, is characterized in that:
Between described first node and described lead-out terminal, possess negative circuit, described output signal is the output signal of described negative circuit.
4. an input circuit, is characterized in that comprising:
The input terminal that input voltage is transfused to;
Export the lead-out terminal based on the output signal of described input voltage;
Grid is transfused to described input voltage and when described input voltage is low level to the first PMOS transistor that first node charges;
Grid be transfused to described input voltage and make the first nmos pass transistor that described first node discharges when described input voltage is high level;
Grid be transfused to described input voltage and make the second nmos pass transistor that described first node discharges when described input voltage is high level;
Block the discharge path from described first node of described second nmos pass transistor when the voltage of described first node is high level second blocks unit; And
The 3rd nmos pass transistor that described first node discharges is made when the voltage of described first node is low level.
5. input circuit as claimed in claim 4, is characterized in that:
Described second blocks unit is made up of nmos pass transistor.
6. the input circuit as described in claim 4 or 5, is characterized in that:
Between described first node and described lead-out terminal, possess negative circuit, described output signal is the output signal of described negative circuit.
7. an input circuit, is characterized in that comprising:
The input terminal that input voltage is transfused to;
Export the lead-out terminal based on the output signal of described input voltage;
Grid is transfused to described input voltage and when described input voltage is low level to the first PMOS transistor that first node charges;
Grid be transfused to described input voltage and make the first nmos pass transistor that described first node discharges when described input voltage is high level;
Grid is transfused to described input voltage and when described input voltage is low level to the second PMOS transistor that described first node charges;
Block described second PMOS transistor when the voltage of described first node is low level and block unit to first of the charge path of described first node;
When the voltage of described first node is high level to the 3rd PMOS transistor that described first node charges;
Grid be transfused to described input voltage and make the second nmos pass transistor that described first node discharges when described input voltage is high level;
Block the discharge path from described first node of described second nmos pass transistor when the voltage of described first node is high level second blocks unit; And
The 3rd nmos pass transistor that described first node discharges is made when the voltage of described first node is low level.
8. input circuit as claimed in claim 7, is characterized in that:
Described first blocks unit is made up of PMOS transistor,
Described second blocks unit is made up of nmos pass transistor.
9. input circuit as claimed in claim 7 or 8, is characterized in that:
Between described first node and described lead-out terminal, possess negative circuit, described output signal is the output signal of described negative circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009-258413 | 2009-11-11 | ||
| JP2009258413A JP5421075B2 (en) | 2009-11-11 | 2009-11-11 | Input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102064694A CN102064694A (en) | 2011-05-18 |
| CN102064694B true CN102064694B (en) | 2015-06-10 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010553872.2A Expired - Fee Related CN102064694B (en) | 2009-11-11 | 2010-11-11 | Input circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20110109364A1 (en) |
| JP (1) | JP5421075B2 (en) |
| KR (1) | KR20110052520A (en) |
| CN (1) | CN102064694B (en) |
| TW (1) | TW201141065A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9152237B1 (en) * | 2014-06-17 | 2015-10-06 | Realtek Semiconductor Corp. | Power bouncing reduction circuit and method thereof |
| JP7063651B2 (en) * | 2018-02-19 | 2022-05-09 | エイブリック株式会社 | Signal detection circuit and signal detection method |
| JP7361474B2 (en) * | 2019-01-31 | 2023-10-16 | エイブリック株式会社 | input circuit |
| JP2022083085A (en) * | 2020-11-24 | 2022-06-03 | 株式会社東芝 | Semiconductor integrated circuit |
| DE102021111796A1 (en) * | 2021-03-19 | 2022-09-22 | Infineon Technologies Ag | HIGH SPEED DIGITAL SIGNAL DRIVER WITH LOW POWER CONSUMPTION |
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| US4539489A (en) * | 1983-06-22 | 1985-09-03 | Motorola, Inc. | CMOS Schmitt trigger circuit |
| US5386153A (en) * | 1993-09-23 | 1995-01-31 | Cypress Semiconductor Corporation | Buffer with pseudo-ground hysteresis |
| US5594361A (en) * | 1994-05-10 | 1997-01-14 | Integrated Device Technology, Inc. | Logic gate with controllable hysteresis and high frequency voltage controlled oscillator |
| CN101385243A (en) * | 2006-02-16 | 2009-03-11 | Nxp股份有限公司 | Transformation of an input signal into a logical output voltage level with a hysteresis behavior |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5877317A (en) * | 1981-11-02 | 1983-05-10 | Matsushita Electric Ind Co Ltd | Schmitt tigger circuit |
| US5349246A (en) * | 1992-12-21 | 1994-09-20 | Sgs-Thomson Microelectronics, Inc. | Input buffer with hysteresis characteristics |
| JPH10229331A (en) * | 1997-02-14 | 1998-08-25 | Texas Instr Japan Ltd | Input circuit |
| JPH10290145A (en) * | 1997-04-14 | 1998-10-27 | Texas Instr Japan Ltd | Hysteresis circuit |
| KR100266011B1 (en) * | 1997-10-01 | 2000-09-15 | 김영환 | Hysteresis input buffer |
| US6433602B1 (en) * | 2000-08-30 | 2002-08-13 | Lattice Semiconductor Corp. | High speed Schmitt Trigger with low supply voltage |
| JP2004096319A (en) * | 2002-08-30 | 2004-03-25 | Mitsubishi Electric Corp | Schmitt trigger circuit |
| US7183826B2 (en) * | 2004-03-11 | 2007-02-27 | Seiko Epson Corporation | High hysteresis width input circuit |
| JP4887111B2 (en) * | 2006-10-12 | 2012-02-29 | オンセミコンダクター・トレーディング・リミテッド | Schmidt circuit |
| JP4983562B2 (en) * | 2007-11-16 | 2012-07-25 | 富士通セミコンダクター株式会社 | Schmidt circuit |
-
2009
- 2009-11-11 JP JP2009258413A patent/JP5421075B2/en not_active Expired - Fee Related
-
2010
- 2010-11-03 TW TW099137779A patent/TW201141065A/en unknown
- 2010-11-10 US US12/943,697 patent/US20110109364A1/en not_active Abandoned
- 2010-11-11 KR KR1020100112127A patent/KR20110052520A/en not_active Application Discontinuation
- 2010-11-11 CN CN201010553872.2A patent/CN102064694B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4539489A (en) * | 1983-06-22 | 1985-09-03 | Motorola, Inc. | CMOS Schmitt trigger circuit |
| US5386153A (en) * | 1993-09-23 | 1995-01-31 | Cypress Semiconductor Corporation | Buffer with pseudo-ground hysteresis |
| US5594361A (en) * | 1994-05-10 | 1997-01-14 | Integrated Device Technology, Inc. | Logic gate with controllable hysteresis and high frequency voltage controlled oscillator |
| CN101385243A (en) * | 2006-02-16 | 2009-03-11 | Nxp股份有限公司 | Transformation of an input signal into a logical output voltage level with a hysteresis behavior |
Also Published As
| Publication number | Publication date |
|---|---|
| US20110109364A1 (en) | 2011-05-12 |
| JP5421075B2 (en) | 2014-02-19 |
| KR20110052520A (en) | 2011-05-18 |
| TW201141065A (en) | 2011-11-16 |
| CN102064694A (en) | 2011-05-18 |
| JP2011103607A (en) | 2011-05-26 |
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