KR20110052520A - 입력 회로 - Google Patents

입력 회로 Download PDF

Info

Publication number
KR20110052520A
KR20110052520A KR1020100112127A KR20100112127A KR20110052520A KR 20110052520 A KR20110052520 A KR 20110052520A KR 1020100112127 A KR1020100112127 A KR 1020100112127A KR 20100112127 A KR20100112127 A KR 20100112127A KR 20110052520 A KR20110052520 A KR 20110052520A
Authority
KR
South Korea
Prior art keywords
input
node
voltage
power supply
hysteresis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020100112127A
Other languages
English (en)
Korean (ko)
Inventor
다로 야마사키
후미야스 우츠노미야
Original Assignee
세이코 인스트루 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세이코 인스트루 가부시키가이샤 filed Critical 세이코 인스트루 가부시키가이샤
Publication of KR20110052520A publication Critical patent/KR20110052520A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
KR1020100112127A 2009-11-11 2010-11-11 입력 회로 Ceased KR20110052520A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009258413A JP5421075B2 (ja) 2009-11-11 2009-11-11 入力回路
JPJP-P-2009-258413 2009-11-11

Publications (1)

Publication Number Publication Date
KR20110052520A true KR20110052520A (ko) 2011-05-18

Family

ID=43973708

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100112127A Ceased KR20110052520A (ko) 2009-11-11 2010-11-11 입력 회로

Country Status (5)

Country Link
US (1) US20110109364A1 (enExample)
JP (1) JP5421075B2 (enExample)
KR (1) KR20110052520A (enExample)
CN (1) CN102064694B (enExample)
TW (1) TW201141065A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9152237B1 (en) * 2014-06-17 2015-10-06 Realtek Semiconductor Corp. Power bouncing reduction circuit and method thereof
JP7063651B2 (ja) * 2018-02-19 2022-05-09 エイブリック株式会社 信号検出回路及び信号検出方法
JP7361474B2 (ja) * 2019-01-31 2023-10-16 エイブリック株式会社 入力回路
JP7548920B2 (ja) 2019-02-27 2024-09-10 ナノモザイク インコーポレイテッド ナノセンサーおよびその使用
JP2022083085A (ja) * 2020-11-24 2022-06-03 株式会社東芝 半導体集積回路
DE102021111796A1 (de) * 2021-03-19 2022-09-22 Infineon Technologies Ag Hochgeschwindigkeitsdigitalsignaltreiber mit niedrigem leistungsverbrauch

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5877317A (ja) * 1981-11-02 1983-05-10 Matsushita Electric Ind Co Ltd シユミツト・トリガ回路
US4539489A (en) * 1983-06-22 1985-09-03 Motorola, Inc. CMOS Schmitt trigger circuit
US5349246A (en) * 1992-12-21 1994-09-20 Sgs-Thomson Microelectronics, Inc. Input buffer with hysteresis characteristics
US5386153A (en) * 1993-09-23 1995-01-31 Cypress Semiconductor Corporation Buffer with pseudo-ground hysteresis
US5459437A (en) * 1994-05-10 1995-10-17 Integrated Device Technology Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
JPH10229331A (ja) * 1997-02-14 1998-08-25 Texas Instr Japan Ltd 入力回路
JPH10290145A (ja) * 1997-04-14 1998-10-27 Texas Instr Japan Ltd ヒステリシス回路
KR100266011B1 (ko) * 1997-10-01 2000-09-15 김영환 히스테리시스입력버퍼
US6433602B1 (en) * 2000-08-30 2002-08-13 Lattice Semiconductor Corp. High speed Schmitt Trigger with low supply voltage
JP2004096319A (ja) * 2002-08-30 2004-03-25 Mitsubishi Electric Corp シュミットトリガ回路
US7183826B2 (en) * 2004-03-11 2007-02-27 Seiko Epson Corporation High hysteresis width input circuit
WO2007093956A1 (en) * 2006-02-16 2007-08-23 Nxp B.V. Transformation of an input signal into a logical output voltage level with a hysteresis behavior
JP4887111B2 (ja) * 2006-10-12 2012-02-29 オンセミコンダクター・トレーディング・リミテッド シュミット回路
JP4983562B2 (ja) * 2007-11-16 2012-07-25 富士通セミコンダクター株式会社 シュミット回路

Also Published As

Publication number Publication date
JP2011103607A (ja) 2011-05-26
CN102064694A (zh) 2011-05-18
CN102064694B (zh) 2015-06-10
JP5421075B2 (ja) 2014-02-19
US20110109364A1 (en) 2011-05-12
TW201141065A (en) 2011-11-16

Similar Documents

Publication Publication Date Title
US9584125B2 (en) Interface circuit
KR101505396B1 (ko) 트랜지스터 스냅백 보호를 탑재한 레벨 시프터 회로
CN103187963B (zh) 电平移位电路和使用电平移位电路的半导体器件
KR930003926B1 (ko) 반도체집적회로
US7511555B2 (en) Level conversion circuit and input-output device using same
JPH0440798B2 (enExample)
KR20010049227A (ko) 레벨조정회로 및 이를 포함하는 데이터 출력회로
KR950004745B1 (ko) 반도체 디지탈 회로
KR20110052520A (ko) 입력 회로
JP5211889B2 (ja) 半導体集積回路
JP2008211707A (ja) 入力回路
KR20040002722A (ko) 레벨 시프터, 반도체 집적 회로 및 정보 처리 시스템
US8405428B2 (en) Semiconductor integrated circuit
US7554361B2 (en) Level shifter and method thereof
WO2007105170A2 (en) Electronic device and integrated circuit
CN108336991B (zh) 电平移位电路
JP4050242B2 (ja) 半導体集積回路装置の入出力回路
JP2017063300A (ja) 入力回路
US7656210B2 (en) Semiconductor integrated circuit
CN114389595B (zh) 电平转换电路
US11070206B2 (en) Logic circuit
KR101622827B1 (ko) 슈미트 트리거 회로를 이용한 논리 게이트
US8330501B1 (en) Dual mode rail-to-rail buffer for low voltage memory
JP2006295322A (ja) レベルシフタ回路
US20070063738A1 (en) CMOS logic circuitry

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20101111

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20150714

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20101111

Comment text: Patent Application

N231 Notification of change of applicant
PN2301 Change of applicant

Patent event date: 20160216

Comment text: Notification of Change of Applicant

Patent event code: PN23011R01D

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20160614

Patent event code: PE09021S01D

E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

Comment text: Final Notice of Reason for Refusal

Patent event date: 20161128

Patent event code: PE09021S02D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20170209

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20161128

Comment text: Final Notice of Reason for Refusal

Patent event code: PE06011S02I

Patent event date: 20160614

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I