JP2011097029A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2011097029A
JP2011097029A JP2010207773A JP2010207773A JP2011097029A JP 2011097029 A JP2011097029 A JP 2011097029A JP 2010207773 A JP2010207773 A JP 2010207773A JP 2010207773 A JP2010207773 A JP 2010207773A JP 2011097029 A JP2011097029 A JP 2011097029A
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JP
Japan
Prior art keywords
plasma
film
oxide film
silicon
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010207773A
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English (en)
Japanese (ja)
Other versions
JP2011097029A5 (https=
Inventor
Yoshihiro Sato
吉宏 佐藤
Toshihiko Shiozawa
俊彦 塩澤
Tatsuo Nishida
辰夫 西田
Yoshihiro Hirota
良浩 廣田
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Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2010207773A priority Critical patent/JP2011097029A/ja
Priority to US13/498,259 priority patent/US20120184107A1/en
Priority to TW099133059A priority patent/TW201125071A/zh
Priority to PCT/JP2010/066886 priority patent/WO2011040426A1/ja
Priority to KR1020127011218A priority patent/KR101380094B1/ko
Publication of JP2011097029A publication Critical patent/JP2011097029A/ja
Publication of JP2011097029A5 publication Critical patent/JP2011097029A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
JP2010207773A 2009-09-30 2010-09-16 半導体装置の製造方法 Pending JP2011097029A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2010207773A JP2011097029A (ja) 2009-09-30 2010-09-16 半導体装置の製造方法
US13/498,259 US20120184107A1 (en) 2009-09-30 2010-09-29 Semiconductor device manufacturing method
TW099133059A TW201125071A (en) 2009-09-30 2010-09-29 Process for manufacturing semiconductor device
PCT/JP2010/066886 WO2011040426A1 (ja) 2009-09-30 2010-09-29 半導体装置の製造方法
KR1020127011218A KR101380094B1 (ko) 2009-09-30 2010-09-29 반도체 장치의 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009227638 2009-09-30
JP2010207773A JP2011097029A (ja) 2009-09-30 2010-09-16 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2011097029A true JP2011097029A (ja) 2011-05-12
JP2011097029A5 JP2011097029A5 (https=) 2013-09-19

Family

ID=43826242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010207773A Pending JP2011097029A (ja) 2009-09-30 2010-09-16 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US20120184107A1 (https=)
JP (1) JP2011097029A (https=)
KR (1) KR101380094B1 (https=)
TW (1) TW201125071A (https=)
WO (1) WO2011040426A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225577A (ja) * 2012-04-20 2013-10-31 Toshiba Corp 半導体装置の製造方法および半導体製造装置
JP2016134614A (ja) * 2015-01-22 2016-07-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2023098896A (ja) * 2018-10-04 2023-07-11 アプライド マテリアルズ インコーポレイテッド 薄型膜処理プロセス

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103258732B (zh) * 2013-05-07 2016-08-24 上海华力微电子有限公司 防止硅衬底表面损伤的方法
US9379132B2 (en) * 2014-10-24 2016-06-28 Sandisk Technologies Inc. NAND memory strings and methods of fabrication thereof
US20160172190A1 (en) * 2014-12-15 2016-06-16 United Microelectronics Corp. Gate oxide formation process
WO2017171488A1 (ko) * 2016-03-31 2017-10-05 주식회사 엘지화학 배리어 필름의 제조 방법
EP3291008A1 (en) * 2016-09-06 2018-03-07 ASML Netherlands B.V. Method and apparatus to monitor a process apparatus
CN111627810B (zh) * 2020-06-05 2022-10-11 合肥晶合集成电路股份有限公司 一种半导体结构及其制造方法
KR102905650B1 (ko) * 2020-06-29 2025-12-30 어플라이드 머티어리얼스, 인코포레이티드 화학 기계적 연마를 위한 스팀 생성의 제어
KR102461496B1 (ko) * 2021-06-03 2022-11-03 주식회사 기가레인 기판 배치 유닛
KR102497494B1 (ko) * 2021-06-03 2023-02-08 주식회사 기가레인 기판 배치 유닛
CN116759325B (zh) * 2023-08-23 2023-11-03 江苏卓胜微电子股份有限公司 用于监控离子注入剂量的阻值监控方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156059A (ja) * 1999-09-16 2001-06-08 Matsushita Electronics Industry Corp 絶縁膜の形成方法および半導体装置の製造方法
JP2004153037A (ja) * 2002-10-31 2004-05-27 Renesas Technology Corp 半導体装置の製造方法
JP2005072358A (ja) * 2003-08-26 2005-03-17 Seiko Epson Corp 半導体装置の製造方法
JP2006222418A (ja) * 2005-01-12 2006-08-24 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2006332555A (ja) * 2005-05-30 2006-12-07 Tokyo Electron Ltd プラズマ処理方法
JP2008053535A (ja) * 2006-08-25 2008-03-06 Toshiba Corp 半導体装置の製造方法及び不揮発性記憶装置の製造方法
JP2008159892A (ja) * 2006-12-25 2008-07-10 Univ Nagoya パターン形成方法、および半導体装置の製造方法
JP2008243973A (ja) * 2007-03-26 2008-10-09 Tokyo Electron Ltd プラズマ処理装置用の載置台及びプラズマ処理装置
WO2009093760A1 (ja) * 2008-01-24 2009-07-30 Tokyo Electron Limited シリコン酸化膜の形成方法、記憶媒体、および、プラズマ処理装置
WO2009099252A1 (ja) * 2008-02-08 2009-08-13 Tokyo Electron Limited 絶縁膜のプラズマ改質処理方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200629421A (en) * 2005-01-12 2006-08-16 Sanyo Electric Co Method of producing semiconductor device
US7799649B2 (en) * 2006-04-13 2010-09-21 Texas Instruments Incorporated Method for forming multi gate devices using a silicon oxide masking layer
JPWO2008026531A1 (ja) * 2006-08-28 2010-01-21 国立大学法人名古屋大学 プラズマ酸化処理方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156059A (ja) * 1999-09-16 2001-06-08 Matsushita Electronics Industry Corp 絶縁膜の形成方法および半導体装置の製造方法
JP2004153037A (ja) * 2002-10-31 2004-05-27 Renesas Technology Corp 半導体装置の製造方法
JP2005072358A (ja) * 2003-08-26 2005-03-17 Seiko Epson Corp 半導体装置の製造方法
JP2006222418A (ja) * 2005-01-12 2006-08-24 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2006332555A (ja) * 2005-05-30 2006-12-07 Tokyo Electron Ltd プラズマ処理方法
JP2008053535A (ja) * 2006-08-25 2008-03-06 Toshiba Corp 半導体装置の製造方法及び不揮発性記憶装置の製造方法
JP2008159892A (ja) * 2006-12-25 2008-07-10 Univ Nagoya パターン形成方法、および半導体装置の製造方法
JP2008243973A (ja) * 2007-03-26 2008-10-09 Tokyo Electron Ltd プラズマ処理装置用の載置台及びプラズマ処理装置
WO2009093760A1 (ja) * 2008-01-24 2009-07-30 Tokyo Electron Limited シリコン酸化膜の形成方法、記憶媒体、および、プラズマ処理装置
WO2009099252A1 (ja) * 2008-02-08 2009-08-13 Tokyo Electron Limited 絶縁膜のプラズマ改質処理方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225577A (ja) * 2012-04-20 2013-10-31 Toshiba Corp 半導体装置の製造方法および半導体製造装置
JP2016134614A (ja) * 2015-01-22 2016-07-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2023098896A (ja) * 2018-10-04 2023-07-11 アプライド マテリアルズ インコーポレイテッド 薄型膜処理プロセス

Also Published As

Publication number Publication date
KR20120069754A (ko) 2012-06-28
KR101380094B1 (ko) 2014-04-01
US20120184107A1 (en) 2012-07-19
WO2011040426A1 (ja) 2011-04-07
TW201125071A (en) 2011-07-16

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