JP2011040703A - Emiノイズ低減印刷回路基板 - Google Patents
Emiノイズ低減印刷回路基板 Download PDFInfo
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- JP2011040703A JP2011040703A JP2009293154A JP2009293154A JP2011040703A JP 2011040703 A JP2011040703 A JP 2011040703A JP 2009293154 A JP2009293154 A JP 2009293154A JP 2009293154 A JP2009293154 A JP 2009293154A JP 2011040703 A JP2011040703 A JP 2011040703A
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- 230000009467 reduction Effects 0.000 title claims abstract description 39
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000005855 radiation Effects 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 26
- 239000000758 substrate Substances 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001684 chronic effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0236—Electromagnetic band-gap structures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】本発明によるEMIノイズ低減印刷回路基板は、帯域阻止周波数特性を有する電磁気バンドギャップ構造が内部に挿入される多層印刷回路基板であって、グラウンド層と電源層が設けられる第1領域と、第1領域の側面に位置し、第1領域の側面から外部に放射されるEMIノイズを遮蔽するように、電磁気バンドギャップ構造が設けられる第2領域と、を含み、電磁気バンドギャップ構造は、第1領域の側面に沿って位置する複数の第1導電板と、第1導電板とは異なる平面上に、第1導電板と交互に配置される複数の第2導電板と、第1導電板と第2導電板を接続するビアと、を含むことを特徴とする。
【選択図】図4
Description
200 第2領域
210 第1導電板
215 連結ライン
220 第2導電板
250 貫通ビア
260 接続ライン
Claims (11)
- 帯域阻止周波数特性を有する電磁気バンドギャップ構造が内部に挿入される多層印刷回路基板であって、
グラウンド層と電源層が設けられる第1領域と、
前記第1領域の側面に位置し、前記第1領域の側面から外部に放射されるEMIノイズを遮蔽するように、前記電磁気バンドギャップ構造が設けられる第2領域と、を含み、
前記電磁気バンドギャップ構造は、
前記第1領域の側面に沿って位置する複数の第1導電板と、
前記第1導電板とは異なる平面上に、前記第1導電板に対して交互に配置される複数の第2導電板と、
前記第1導電板と前記第2導電板を接続するビアと、
を含むことを特徴とするEMIノイズ低減印刷回路基板。 - 前記第1導電板と前記第2導電板は、互いの両端部がオーバーラップするように配置されることを特徴とする請求項1に記載のEMIノイズ低減印刷回路。
- オーバーラップした前記第1導電板と前記第2導電板の端部は前記ビアを介して互いに接続されることを特徴とする請求項2に記載のEMIノイズ低減印刷回路。
- 前記第1領域と前記第2領域が4層以上の多層で形成され、
前記ビアは前記第2領域の上下を貫通する貫通ビアであることを特徴とする請求項1に記載のEMIノイズ低減印刷回路基板。 - 前記第2領域を形成する多層のうち上下方向に対向する各2つの導電板は、互いの両端部がオーバーラップするように配置されることを特徴とする請求項4に記載のEMIノイズ低減印刷回路。
- オーバーラップした前記各2つの導電板は、前記ビアを介して互いに接続されることを特徴とする請求項5に記載のEMIノイズ低減印刷回路。
- 前記ビアがブラインドビアであることを特徴とする請求項1に記載のEMIノイズ低減印刷回路基板。
- 前記第1導電板と前記第2導電板のうち少なくとも何れか1つが、
前記第1領域のエッジ形状に対応して屈曲された形状を有することを特徴とする請求項1から7の何れか1項に記載のEMIノイズ低減印刷回路基板。 - 前記複数の第1導電板のうち互いに隣接する少なくとも一対は、連結ラインを介して電気的に接続することを特徴とする請求項1から8の何れか1項に記載のEMIノイズ低減印刷回路基板。
- 前記第1導電板は、接続ラインを介して前記グラウンド層に電気的に接続されることを特徴とする請求項1から9の何れか1項に記載のEMIノイズ低減印刷回路基板。
- 前記第2領域が、前記第1領域の側面の一部だけに選択的に配置されることを特徴とする請求項1から10の何れか1項に記載のEMIノイズ低減印刷回路基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2009-0073444 | 2009-08-10 | ||
KR1020090073444A KR101072591B1 (ko) | 2009-08-10 | 2009-08-10 | Emi 노이즈 저감 인쇄회로기판 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011040703A true JP2011040703A (ja) | 2011-02-24 |
JP5164965B2 JP5164965B2 (ja) | 2013-03-21 |
Family
ID=43533957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009293154A Expired - Fee Related JP5164965B2 (ja) | 2009-08-10 | 2009-12-24 | Emiノイズ低減印刷回路基板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8258408B2 (ja) |
JP (1) | JP5164965B2 (ja) |
KR (1) | KR101072591B1 (ja) |
TW (1) | TWI454189B (ja) |
Cited By (4)
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JP2014150102A (ja) * | 2013-01-31 | 2014-08-21 | Shinko Electric Ind Co Ltd | 半導体装置 |
US9583818B2 (en) | 2014-01-30 | 2017-02-28 | Canon Kabushiki Kaisha | Metamaterial |
JP2017084957A (ja) * | 2015-10-28 | 2017-05-18 | 三菱電機株式会社 | 電磁波減衰構造体及び電磁シールド構造体 |
US10687414B2 (en) | 2017-06-26 | 2020-06-16 | Ricoh Company, Ltd. | Circuit board |
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- 2009-08-10 KR KR1020090073444A patent/KR101072591B1/ko active IP Right Grant
- 2009-12-22 US US12/654,545 patent/US8258408B2/en not_active Expired - Fee Related
- 2009-12-24 JP JP2009293154A patent/JP5164965B2/ja not_active Expired - Fee Related
- 2009-12-31 TW TW098146469A patent/TWI454189B/zh not_active IP Right Cessation
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Cited By (4)
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JP2014150102A (ja) * | 2013-01-31 | 2014-08-21 | Shinko Electric Ind Co Ltd | 半導体装置 |
US9583818B2 (en) | 2014-01-30 | 2017-02-28 | Canon Kabushiki Kaisha | Metamaterial |
JP2017084957A (ja) * | 2015-10-28 | 2017-05-18 | 三菱電機株式会社 | 電磁波減衰構造体及び電磁シールド構造体 |
US10687414B2 (en) | 2017-06-26 | 2020-06-16 | Ricoh Company, Ltd. | Circuit board |
Also Published As
Publication number | Publication date |
---|---|
KR101072591B1 (ko) | 2011-10-11 |
TW201106813A (en) | 2011-02-16 |
US20110031007A1 (en) | 2011-02-10 |
TWI454189B (zh) | 2014-09-21 |
US8258408B2 (en) | 2012-09-04 |
JP5164965B2 (ja) | 2013-03-21 |
KR20110015971A (ko) | 2011-02-17 |
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