JP2010525609A5 - - Google Patents

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Publication number
JP2010525609A5
JP2010525609A5 JP2010506376A JP2010506376A JP2010525609A5 JP 2010525609 A5 JP2010525609 A5 JP 2010525609A5 JP 2010506376 A JP2010506376 A JP 2010506376A JP 2010506376 A JP2010506376 A JP 2010506376A JP 2010525609 A5 JP2010525609 A5 JP 2010525609A5
Authority
JP
Japan
Prior art keywords
mesa
layer
forming
conductor layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010506376A
Other languages
English (en)
Japanese (ja)
Other versions
JP5280434B2 (ja
JP2010525609A (ja
Filing date
Publication date
Priority claimed from US11/738,683 external-priority patent/US8039339B2/en
Application filed filed Critical
Publication of JP2010525609A publication Critical patent/JP2010525609A/ja
Publication of JP2010525609A5 publication Critical patent/JP2010525609A5/ja
Application granted granted Critical
Publication of JP5280434B2 publication Critical patent/JP5280434B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010506376A 2007-04-23 2008-04-04 半導体デバイスにおける分離層の形成 Expired - Fee Related JP5280434B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/738,683 2007-04-23
US11/738,683 US8039339B2 (en) 2007-04-23 2007-04-23 Separate layer formation in a semiconductor device
PCT/US2008/059352 WO2008130818A1 (en) 2007-04-23 2008-04-04 Separate layer formation in a semiconductor device

Publications (3)

Publication Number Publication Date
JP2010525609A JP2010525609A (ja) 2010-07-22
JP2010525609A5 true JP2010525609A5 (enExample) 2011-05-26
JP5280434B2 JP5280434B2 (ja) 2013-09-04

Family

ID=39872628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010506376A Expired - Fee Related JP5280434B2 (ja) 2007-04-23 2008-04-04 半導体デバイスにおける分離層の形成

Country Status (5)

Country Link
US (1) US8039339B2 (enExample)
JP (1) JP5280434B2 (enExample)
CN (1) CN101675512A (enExample)
TW (1) TWI442511B (enExample)
WO (1) WO2008130818A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016101545B4 (de) * 2016-01-28 2020-10-08 Infineon Technologies Dresden Gmbh Verfahren zum herstellen einer halbleitervorrichtung mit silicidschichten und eine halbleitervorrichtung
CN113078067B (zh) * 2021-03-30 2023-04-28 电子科技大学 一种沟槽分离栅器件的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447874A (en) * 1994-07-29 1995-09-05 Grivna; Gordon Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish
US6013551A (en) * 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6027961A (en) * 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6204103B1 (en) * 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
US6262456B1 (en) * 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
JP3613113B2 (ja) * 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6444512B1 (en) * 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
JP2002009171A (ja) * 2000-06-22 2002-01-11 Fujitsu Ltd 半導体装置の製造方法
US6627510B1 (en) * 2002-03-29 2003-09-30 Sharp Laboratories Of America, Inc. Method of making self-aligned shallow trench isolation
TW544840B (en) * 2002-06-27 2003-08-01 Intelligent Sources Dev Corp A stack-type DRAM memory structure and its manufacturing method
US6846734B2 (en) * 2002-11-20 2005-01-25 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
US6919647B2 (en) * 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7018887B1 (en) * 2004-03-01 2006-03-28 Advanced Micro Devices, Inc. Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode
US7157378B2 (en) * 2004-07-06 2007-01-02 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7422936B2 (en) * 2004-08-25 2008-09-09 Intel Corporation Facilitating removal of sacrificial layers via implantation to form replacement metal gates
US7074664B1 (en) * 2005-03-29 2006-07-11 Freescale Semiconductor, Inc. Dual metal gate electrode semiconductor fabrication process and structure thereof

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