JP2015073095A5 - - Google Patents

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Publication number
JP2015073095A5
JP2015073095A5 JP2014183997A JP2014183997A JP2015073095A5 JP 2015073095 A5 JP2015073095 A5 JP 2015073095A5 JP 2014183997 A JP2014183997 A JP 2014183997A JP 2014183997 A JP2014183997 A JP 2014183997A JP 2015073095 A5 JP2015073095 A5 JP 2015073095A5
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JP
Japan
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conductor
forming
dielectric layer
filling
space
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JP2014183997A
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English (en)
Japanese (ja)
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JP6226839B2 (ja
JP2015073095A (ja
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Priority claimed from US14/045,680 external-priority patent/US9012278B2/en
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JP2014183997A 2013-10-03 2014-09-10 ワイヤ−ベース半導体装置を製造する方法 Active JP6226839B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/045,680 US9012278B2 (en) 2013-10-03 2013-10-03 Method of making a wire-based semiconductor device
US14/045,680 2013-10-03

Publications (3)

Publication Number Publication Date
JP2015073095A JP2015073095A (ja) 2015-04-16
JP2015073095A5 true JP2015073095A5 (enExample) 2017-06-08
JP6226839B2 JP6226839B2 (ja) 2017-11-08

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JP2014183997A Active JP6226839B2 (ja) 2013-10-03 2014-09-10 ワイヤ−ベース半導体装置を製造する方法

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US (2) US9012278B2 (enExample)
JP (1) JP6226839B2 (enExample)
KR (1) KR101824155B1 (enExample)
TW (1) TWI609491B (enExample)

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WO2022153676A1 (ja) * 2021-01-15 2022-07-21 国立大学法人東北大学 半導体デバイス、集積回路及びその製造方法
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