KR101824155B1 - 와이어에 기초한 반도체 장치의 형성 방법 - Google Patents

와이어에 기초한 반도체 장치의 형성 방법 Download PDF

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KR101824155B1
KR101824155B1 KR1020140133332A KR20140133332A KR101824155B1 KR 101824155 B1 KR101824155 B1 KR 101824155B1 KR 1020140133332 A KR1020140133332 A KR 1020140133332A KR 20140133332 A KR20140133332 A KR 20140133332A KR 101824155 B1 KR101824155 B1 KR 101824155B1
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forming
dielectric layer
conductor
filling
dielectric
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KR20150039698A (ko
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치 시에
블라디미르 마츠카오우샨
얀 빌럼 마스
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에이에스엠 아이피 홀딩 비.브이.
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
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    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
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    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/122—Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
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    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
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    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
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  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020140133332A 2013-10-03 2014-10-02 와이어에 기초한 반도체 장치의 형성 방법 Active KR101824155B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/045,680 US9012278B2 (en) 2013-10-03 2013-10-03 Method of making a wire-based semiconductor device
US14/045,680 2013-10-03

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KR20150039698A KR20150039698A (ko) 2015-04-13
KR101824155B1 true KR101824155B1 (ko) 2018-02-01

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US (2) US9012278B2 (enExample)
JP (1) JP6226839B2 (enExample)
KR (1) KR101824155B1 (enExample)
TW (1) TWI609491B (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9012278B2 (en) * 2013-10-03 2015-04-21 Asm Ip Holding B.V. Method of making a wire-based semiconductor device
WO2015147865A1 (en) * 2014-03-28 2015-10-01 Intel Corporation Aspect ratio trapping (art) for fabricating vertical semiconductor devices
JP5692884B1 (ja) * 2014-08-19 2015-04-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Ｓｇｔを有する半導体装置の製造方法
US9871111B2 (en) * 2014-09-18 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20160268256A1 (en) * 2015-03-13 2016-09-15 Qualcomm Incorporated Complementary metal-oxide semiconductor (cmos) transistor and tunnel field-effect transistor (tfet) on a single substrate
US9972622B2 (en) * 2015-05-13 2018-05-15 Imec Vzw Method for manufacturing a CMOS device and associated device
TWI566417B (zh) * 2015-12-04 2017-01-11 財團法人工業技術研究院 ｐ型金屬氧化物半導體材料與電晶體
US9882047B2 (en) * 2016-02-01 2018-01-30 International Business Machines Corporation Self-aligned replacement metal gate spacerless vertical field effect transistor
US10043796B2 (en) 2016-02-01 2018-08-07 Qualcomm Incorporated Vertically stacked nanowire field effect transistors
CN109643725B (zh) * 2016-08-08 2022-07-29 东京毅力科创株式会社 三维半导体器件及制造方法
US10361300B2 (en) 2017-02-28 2019-07-23 International Business Machines Corporation Asymmetric vertical device
CN108878521B (zh) * 2017-05-09 2021-10-15 中芯国际集成电路制造(上海)有限公司 垂直隧穿场效应晶体管及其形成方法
US9960272B1 (en) * 2017-05-16 2018-05-01 International Business Machines Corporation Bottom contact resistance reduction on VFET
US10475808B2 (en) * 2017-08-30 2019-11-12 Macronix International Co., Ltd. Three dimensional memory device and method for fabricating the same
CN109494249B (zh) * 2017-09-11 2022-05-24 联华电子股份有限公司 半导体元件及其制造方法
KR102337408B1 (ko) * 2017-09-13 2021-12-10 삼성전자주식회사 수직 채널을 가지는 반도체 소자 및 그 제조 방법
CN108511344B (zh) * 2018-02-09 2021-01-22 中国科学院微电子研究所 垂直纳米线晶体管与其制作方法
US10424653B1 (en) * 2018-05-21 2019-09-24 International Business Machines Corporation Vertical transport field effect transistor on silicon with defined junctions
US10833079B2 (en) 2019-01-02 2020-11-10 International Business Machines Corporation Dual transport orientation for stacked vertical transport field-effect transistors
US11164791B2 (en) * 2019-02-25 2021-11-02 International Business Machines Corporation Contact formation for stacked vertical transport field-effect transistors
CN110021603B (zh) * 2019-04-11 2021-09-14 德淮半导体有限公司 半导体结构及其形成方法
US11075266B2 (en) 2019-04-29 2021-07-27 International Business Machines Corporation Vertically stacked fin semiconductor devices
US11646205B2 (en) * 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
US11202912B2 (en) 2019-12-19 2021-12-21 Medtronic, Inc. Posture-based control of electrical stimulation therapy
US11179567B2 (en) 2019-12-19 2021-11-23 Medtronic, Inc. Hysteresis compensation for detection of ECAPs
US11439825B2 (en) 2019-12-19 2022-09-13 Medtronic, Inc. Determining posture state from ECAPs
US12097373B2 (en) 2020-06-10 2024-09-24 Medtronic, Inc. Control policy settings for electrical stimulation therapy
US11857793B2 (en) 2020-06-10 2024-01-02 Medtronic, Inc. Managing storage of sensed information
WO2022153676A1 (ja) * 2021-01-15 2022-07-21 国立大学法人東北大学 半導体デバイス、集積回路及びその製造方法
US20220359208A1 (en) * 2021-05-07 2022-11-10 Applied Materials, Inc. Process integration to reduce contact resistance in semiconductor device
US20250169091A1 (en) 2023-11-21 2025-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Radical Treatment in Supercritical Fluid for Gate Dielectric Quality Improvement to CFET Structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050048709A1 (en) 2001-09-21 2005-03-03 Layman Paul Arthur Multiple operating voltage vertical replacement-gate (VRG) transistor
US20110012085A1 (en) 2007-09-24 2011-01-20 International Business Machines Corporation Methods of manufacture of vertical nanowire fet devices

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450472A (en) 1981-03-02 1984-05-22 The Board Of Trustees Of The Leland Stanford Junior University Method and means for improved heat removal in compact semiconductor integrated circuits and similar devices utilizing coolant chambers and microscopic channels
US4938742A (en) 1988-02-04 1990-07-03 Smits Johannes G Piezoelectric micropump with microvalves
JP3325072B2 (ja) * 1992-03-02 2002-09-17 モトローラ・インコーポレイテッド 半導体メモリ装置
US5241450A (en) 1992-03-13 1993-08-31 The United States Of America As Represented By The United States Department Of Energy Three dimensional, multi-chip module
US5218515A (en) 1992-03-13 1993-06-08 The United States Of America As Represented By The United States Department Of Energy Microchannel cooling of face down bonded chips
US5461003A (en) 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5619177A (en) 1995-01-27 1997-04-08 Mjb Company Shape memory alloy microactuator having an electrostatic force and heating means
US5777292A (en) 1996-02-01 1998-07-07 Room Temperature Superconductors Inc. Materials having high electrical conductivity at room teperatures and methods for making same
US5929476A (en) * 1996-06-21 1999-07-27 Prall; Kirk Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors
US5763951A (en) 1996-07-22 1998-06-09 Northrop Grumman Corporation Non-mechanical magnetic pump for liquid cooling
WO1998003997A1 (en) 1996-07-22 1998-01-29 Northrop Grumman Corporation Closed loop liquid cooling within rf modules
US5801442A (en) 1996-07-22 1998-09-01 Northrop Grumman Corporation Microchannel cooling of high power semiconductor devices
FR2754391B1 (fr) 1996-10-08 1999-04-16 Sgs Thomson Microelectronics Structure de contact a facteur de forme eleve pour circuits integres
US5901037A (en) 1997-06-18 1999-05-04 Northrop Grumman Corporation Closed loop liquid cooling for semiconductor RF amplifier modules
US6272169B1 (en) 1998-06-09 2001-08-07 Advanced Micro Devices, Inc. Software based modems that interact with the computing enviroment
US6060383A (en) 1998-08-10 2000-05-09 Nogami; Takeshi Method for making multilayered coaxial interconnect structure
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
US6027975A (en) * 1998-08-28 2000-02-22 Lucent Technologies Inc. Process for fabricating vertical transistors
US6406995B1 (en) 1998-09-30 2002-06-18 Intel Corporation Pattern-sensitive deposition for damascene processing
US6329118B1 (en) 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
US6291353B1 (en) 1999-08-19 2001-09-18 International Business Machines Corporation Lateral patterning
US6727169B1 (en) 1999-10-15 2004-04-27 Asm International, N.V. Method of making conformal lining layers for damascene metallization
EP1266054B1 (en) 2000-03-07 2006-12-20 Asm International N.V. Graded thin films
US6759325B2 (en) 2000-05-15 2004-07-06 Asm Microchemistry Oy Sealing porous structures
US6482733B2 (en) 2000-05-15 2002-11-19 Asm Microchemistry Oy Protective layers prior to alternating layer deposition
SG105459A1 (en) 2000-07-24 2004-08-27 Micron Technology Inc Mems heat pumps for integrated circuit heat dissipation
US6569754B2 (en) 2000-08-24 2003-05-27 The Regents Of The University Of Michigan Method for making a module including a microplatform
US6770122B2 (en) 2001-12-12 2004-08-03 E. I. Du Pont De Nemours And Company Copper deposition using copper formate complexes
US6716693B1 (en) 2003-03-27 2004-04-06 Chartered Semiconductor Manufacturing Ltd. Method of forming a surface coating layer within an opening within a body by atomic layer deposition
US7018917B2 (en) 2003-11-20 2006-03-28 Asm International N.V. Multilayer metallization
US7241655B2 (en) * 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
FR2897204B1 (fr) * 2006-02-07 2008-05-30 Ecole Polytechnique Etablissem Structure de transistor vertical et procede de fabrication
JP2011228596A (ja) * 2010-04-22 2011-11-10 Shirado Takehide 半導体装置及びその製造方法
US9012278B2 (en) * 2013-10-03 2015-04-21 Asm Ip Holding B.V. Method of making a wire-based semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050048709A1 (en) 2001-09-21 2005-03-03 Layman Paul Arthur Multiple operating voltage vertical replacement-gate (VRG) transistor
US20110012085A1 (en) 2007-09-24 2011-01-20 International Business Machines Corporation Methods of manufacture of vertical nanowire fet devices

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