TWI442511B - 半導體裝置中之分層形成 - Google Patents

半導體裝置中之分層形成 Download PDF

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Publication number
TWI442511B
TWI442511B TW097114353A TW97114353A TWI442511B TW I442511 B TWI442511 B TW I442511B TW 097114353 A TW097114353 A TW 097114353A TW 97114353 A TW97114353 A TW 97114353A TW I442511 B TWI442511 B TW I442511B
Authority
TW
Taiwan
Prior art keywords
layer
forming
mesa
metal
semiconductor
Prior art date
Application number
TW097114353A
Other languages
English (en)
Chinese (zh)
Other versions
TW200908211A (en
Inventor
葛倫特 約翰Ｍ
沙瑪維丹 斯里坎斯Ｂ
凡凱森 蘇瑞許
Original Assignee
飛思卡爾半導體公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 飛思卡爾半導體公司 filed Critical 飛思卡爾半導體公司
Publication of TW200908211A publication Critical patent/TW200908211A/zh
Application granted granted Critical
Publication of TWI442511B publication Critical patent/TWI442511B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
TW097114353A 2007-04-23 2008-04-18 半導體裝置中之分層形成 TWI442511B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/738,683 US8039339B2 (en) 2007-04-23 2007-04-23 Separate layer formation in a semiconductor device

Publications (2)

Publication Number Publication Date
TW200908211A TW200908211A (en) 2009-02-16
TWI442511B true TWI442511B (zh) 2014-06-21

Family

ID=39872628

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097114353A TWI442511B (zh) 2007-04-23 2008-04-18 半導體裝置中之分層形成

Country Status (5)

Country Link
US (1) US8039339B2 (enExample)
JP (1) JP5280434B2 (enExample)
CN (1) CN101675512A (enExample)
TW (1) TWI442511B (enExample)
WO (1) WO2008130818A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016101545B4 (de) 2016-01-28 2020-10-08 Infineon Technologies Dresden Gmbh Verfahren zum herstellen einer halbleitervorrichtung mit silicidschichten und eine halbleitervorrichtung
CN113078067B (zh) * 2021-03-30 2023-04-28 电子科技大学 一种沟槽分离栅器件的制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447874A (en) * 1994-07-29 1995-09-05 Grivna; Gordon Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish
US6013551A (en) 1997-09-26 2000-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US6027961A (en) 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6204103B1 (en) 1998-09-18 2001-03-20 Intel Corporation Process to make complementary silicide metal gates for CMOS technology
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
JP3613113B2 (ja) * 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6444512B1 (en) 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
JP2002009171A (ja) * 2000-06-22 2002-01-11 Fujitsu Ltd 半導体装置の製造方法
US6627510B1 (en) 2002-03-29 2003-09-30 Sharp Laboratories Of America, Inc. Method of making self-aligned shallow trench isolation
TW544840B (en) * 2002-06-27 2003-08-01 Intelligent Sources Dev Corp A stack-type DRAM memory structure and its manufacturing method
US6846734B2 (en) 2002-11-20 2005-01-25 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
US6919647B2 (en) * 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7018887B1 (en) 2004-03-01 2006-03-28 Advanced Micro Devices, Inc. Dual metal CMOS transistors with silicon-metal-silicon stacked gate electrode
US7157378B2 (en) 2004-07-06 2007-01-02 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7422936B2 (en) 2004-08-25 2008-09-09 Intel Corporation Facilitating removal of sacrificial layers via implantation to form replacement metal gates
US7074664B1 (en) 2005-03-29 2006-07-11 Freescale Semiconductor, Inc. Dual metal gate electrode semiconductor fabrication process and structure thereof

Also Published As

Publication number Publication date
JP5280434B2 (ja) 2013-09-04
US8039339B2 (en) 2011-10-18
WO2008130818A1 (en) 2008-10-30
CN101675512A (zh) 2010-03-17
US20080261374A1 (en) 2008-10-23
JP2010525609A (ja) 2010-07-22
TW200908211A (en) 2009-02-16

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