JP2010500757A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP2010500757A JP2010500757A JP2009523866A JP2009523866A JP2010500757A JP 2010500757 A JP2010500757 A JP 2010500757A JP 2009523866 A JP2009523866 A JP 2009523866A JP 2009523866 A JP2009523866 A JP 2009523866A JP 2010500757 A JP2010500757 A JP 2010500757A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【選択図】図7
Description
106、206 半導体ダイ
110、210 ハウジング
112、212 リード
130 ボイド
200 半導体装置
202 導電性取着領域
208 層間材
220 ベタ部分
222 多孔部分
800 MOSFETダイ
810、830、850 半田
820 第1リードフレーム
840 第2リードフレーム
880 パッケージ材料
890 銀ペースト
Claims (20)
- 基板に実装可能な半導体装置であって、該半導体装置には:
半導体ダイと;
第1取着面及び第2取着面を有する導電性取着領域であって、前記第1取着面を前記半導体ダイと電気的に導通するよう設ける該導電性取着領域と;
前記導電性取着領域の前記第2取着面に形成した層間材であって、熱伝導、誘電性材料とする該層間材と;
前記半導体ダイ及び前記層間材を少なくとも部分的に包囲するハウジングと、
を備えること、を特徴とする半導体装置。 - 前記半導体装置は、電力用半導体装置を含むこと、を特徴とする請求項1に記載の半導体装置。
- 前記電力用半導体装置は、整流器を含むこと、を特徴とする請求項2に記載の半導体装置。
- 前記整流器は、ブリッジ整流器を含むこと、を特徴とする請求項3に記載の半導体装置。
- 前記半導体装置は、表面実装可能な装置を含むこと、を特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は、スルーホール実装可能な装置を含むこと、を特徴とする請求項1に記載の半導体装置。
- 前記半導体装置は、集積回路を含むこと、を特徴とする請求項1に記載の半導体装置。
- 前記集積回路は、チップスケールパッケージを含むこと、を特徴とする請求項7に記載の半導体装置。
- 前記導電性取着領域は、銅パッド、半田ボール、リード、リードフレーム、及びリードフレーム端子を含むこと、を特徴とする請求項8に記載の半導体装置。
- 前記層間材を、熱伝導性接着剤とすること、を特徴とする請求項1に記載の半導体装置。
- 前記層間材は、スクリーン印刷層を含むこと、を特徴とする請求項1に記載の半導体装置。
- 前記ハウジングは、モールドコンパウンドを含むこと、を特徴とする請求項1に記載の半導体装置。
- 基板に実装可能な半導体装置を製造する方法であって、該方法には:
半導体ダイを、導電性取着領域の第1取着部分と電気的に導通するよう設けること;
誘電、熱伝導性層間材を前記導電性取着領域の第2取着部分に塗布すること;
少なくとも部分的に、前記ダイ及び前記層間材を包囲するハウジングを設けること、
を含むことを特徴とする方法。 - 前記ハウジングを、前記半導体装置の外装パッケージを形成するように、成形すること、を更に含むことを特徴とする請求項13に記載の半導体装置を製造する方法。
- 前記層間材を熱伝導性とすること、を特徴とする請求項13に記載の方法。
- 前記層間材を、スクリーン印刷工程により塗布すること、を特徴とする請求項13に記載の方法。
- 前記半導体装置は、表面実装可能な装置を含むこと、を特徴とする請求項13に記載の方法。
- 前記半導体装置は、スルーホール実装可能な装置を含むこと、を特徴とする請求項13に記載の方法。
- 前記導電性取着領域は、銅パッド、半田ボール、リード、リードフレーム、及びリードフレーム端子の1つを含むこと、を特徴とする請求項13に記載の方法。
- 前記半導体装置は、電力用半導体装置を含むこと、を特徴とする請求項13に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US83732906P | 2006-08-11 | 2006-08-11 | |
US11/827,041 US7719096B2 (en) | 2006-08-11 | 2007-07-09 | Semiconductor device and method for manufacturing a semiconductor device |
PCT/US2007/017849 WO2008021272A2 (en) | 2006-08-11 | 2007-08-10 | Semiconductor device and method for manufacturing a semiconductor device |
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JP2010500757A true JP2010500757A (ja) | 2010-01-07 |
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JP2009523866A Pending JP2010500757A (ja) | 2006-08-11 | 2007-08-10 | 半導体装置及び半導体装置の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7719096B2 (ja) |
EP (1) | EP2070113B1 (ja) |
JP (1) | JP2010500757A (ja) |
CN (1) | CN101501841B (ja) |
TW (1) | TWI419271B (ja) |
WO (1) | WO2008021272A2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8421214B2 (en) * | 2007-10-10 | 2013-04-16 | Vishay General Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device |
TWI659509B (zh) * | 2017-12-19 | 2019-05-11 | 英屬開曼群島商鳳凰先驅股份有限公司 | 電子封裝件及其製法 |
RU2697458C1 (ru) * | 2018-09-19 | 2019-08-14 | Акционерное общество "Научно-производственный центр "Алмаз-Фазотрон" | Способ изготовления герметичного электронного модуля |
Citations (2)
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JPS58440U (ja) * | 1981-06-25 | 1983-01-05 | 富士通株式会社 | プラスチツクパツケ−ジ |
JPS6365655A (ja) * | 1986-09-05 | 1988-03-24 | Nec Corp | 樹脂封止型半導体装置 |
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US4510519A (en) * | 1982-03-26 | 1985-04-09 | Motorola, Inc. | Electrically isolated semiconductor power device |
JPS59135753A (ja) * | 1983-01-25 | 1984-08-04 | Toshiba Corp | 半導体装置とその製造方法 |
JPH0758746B2 (ja) * | 1985-02-27 | 1995-06-21 | 株式会社東芝 | 樹脂封止型半導体装置 |
US5174941A (en) * | 1988-06-02 | 1992-12-29 | Primtec | Injection-molding product wall-thickness control methods |
JPH02198160A (ja) * | 1989-01-27 | 1990-08-06 | Hitachi Ltd | 樹脂封止半導体装置 |
US5326243A (en) * | 1992-06-25 | 1994-07-05 | Fierkens Richard H J | Compression-cavity mold for plastic encapsulation of thin-package integrated circuit device |
JPH0621317A (ja) * | 1992-07-02 | 1994-01-28 | Seiko Epson Corp | 半導体パッケージの製造方法 |
US6058602A (en) * | 1998-09-21 | 2000-05-09 | Integrated Packaging Assembly Corporation | Method for encapsulating IC packages with diamond substrate |
US6054760A (en) * | 1996-12-23 | 2000-04-25 | Scb Technologies Inc. | Surface-connectable semiconductor bridge elements and devices including the same |
US6019037A (en) * | 1998-08-03 | 2000-02-01 | Micron Technology, Inc. | Method for screen printing patterns on a target object |
US6063646A (en) * | 1998-10-06 | 2000-05-16 | Japan Rec Co., Ltd. | Method for production of semiconductor package |
US6306331B1 (en) * | 1999-03-24 | 2001-10-23 | International Business Machines Corporation | Ultra mold for encapsulating very thin packages |
KR100342589B1 (ko) * | 1999-10-01 | 2002-07-04 | 김덕중 | 반도체 전력 모듈 및 그 제조 방법 |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
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JP3689694B2 (ja) * | 2002-12-27 | 2005-08-31 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
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US20070013053A1 (en) | 2005-07-12 | 2007-01-18 | Peter Chou | Semiconductor device and method for manufacturing a semiconductor device |
-
2007
- 2007-07-09 US US11/827,041 patent/US7719096B2/en active Active
- 2007-07-31 TW TW096128003A patent/TWI419271B/zh active
- 2007-08-10 WO PCT/US2007/017849 patent/WO2008021272A2/en active Application Filing
- 2007-08-10 JP JP2009523866A patent/JP2010500757A/ja active Pending
- 2007-08-10 CN CN2007800300019A patent/CN101501841B/zh active Active
- 2007-08-10 EP EP07811265.3A patent/EP2070113B1/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58440U (ja) * | 1981-06-25 | 1983-01-05 | 富士通株式会社 | プラスチツクパツケ−ジ |
JPS6365655A (ja) * | 1986-09-05 | 1988-03-24 | Nec Corp | 樹脂封止型半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
TWI419271B (zh) | 2013-12-11 |
US20080036072A1 (en) | 2008-02-14 |
EP2070113A4 (en) | 2011-05-04 |
WO2008021272A3 (en) | 2008-07-31 |
EP2070113B1 (en) | 2016-10-05 |
EP2070113A2 (en) | 2009-06-17 |
US7719096B2 (en) | 2010-05-18 |
CN101501841B (zh) | 2011-07-06 |
TW200826260A (en) | 2008-06-16 |
WO2008021272A2 (en) | 2008-02-21 |
CN101501841A (zh) | 2009-08-05 |
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