JP2010267328A5 - - Google Patents

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Publication number
JP2010267328A5
JP2010267328A5 JP2009117889A JP2009117889A JP2010267328A5 JP 2010267328 A5 JP2010267328 A5 JP 2010267328A5 JP 2009117889 A JP2009117889 A JP 2009117889A JP 2009117889 A JP2009117889 A JP 2009117889A JP 2010267328 A5 JP2010267328 A5 JP 2010267328A5
Authority
JP
Japan
Prior art keywords
voltage
circuit
transistor
semiconductor memory
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009117889A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010267328A (ja
JP5465919B2 (ja
Filing date
Publication date
Priority claimed from JP2009117889A external-priority patent/JP5465919B2/ja
Priority to JP2009117889A priority Critical patent/JP5465919B2/ja
Application filed filed Critical
Priority to US12/769,141 priority patent/US8279691B2/en
Publication of JP2010267328A publication Critical patent/JP2010267328A/ja
Publication of JP2010267328A5 publication Critical patent/JP2010267328A5/ja
Priority to US13/600,412 priority patent/US8482999B2/en
Priority to US13/918,425 priority patent/US8681577B2/en
Priority to US14/147,166 priority patent/US8811103B2/en
Publication of JP5465919B2 publication Critical patent/JP5465919B2/ja
Application granted granted Critical
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009117889A 2009-05-14 2009-05-14 半導体集積装置 Active JP5465919B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009117889A JP5465919B2 (ja) 2009-05-14 2009-05-14 半導体集積装置
US12/769,141 US8279691B2 (en) 2009-05-14 2010-04-28 Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage
US13/600,412 US8482999B2 (en) 2009-05-14 2012-08-31 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage
US13/918,425 US8681577B2 (en) 2009-05-14 2013-06-14 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage
US14/147,166 US8811103B2 (en) 2009-05-14 2014-01-03 Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009117889A JP5465919B2 (ja) 2009-05-14 2009-05-14 半導体集積装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013088213A Division JP5710681B2 (ja) 2013-04-19 2013-04-19 半導体集積装置

Publications (3)

Publication Number Publication Date
JP2010267328A JP2010267328A (ja) 2010-11-25
JP2010267328A5 true JP2010267328A5 (enExample) 2012-04-05
JP5465919B2 JP5465919B2 (ja) 2014-04-09

Family

ID=43068409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009117889A Active JP5465919B2 (ja) 2009-05-14 2009-05-14 半導体集積装置

Country Status (2)

Country Link
US (4) US8279691B2 (enExample)
JP (1) JP5465919B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5465919B2 (ja) 2009-05-14 2014-04-09 ルネサスエレクトロニクス株式会社 半導体集積装置
JP5886496B2 (ja) 2011-05-20 2016-03-16 株式会社半導体エネルギー研究所 半導体装置
TWI573136B (zh) 2011-05-20 2017-03-01 半導體能源研究所股份有限公司 儲存裝置及信號處理電路
TWI570719B (zh) * 2011-05-20 2017-02-11 半導體能源研究所股份有限公司 儲存裝置及信號處理電路
US9111638B2 (en) * 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. SRAM bit cell with reduced bit line pre-charge voltage
TWI489444B (zh) * 2012-07-17 2015-06-21 Etron Technology Inc 應用於嵌入式顯示埠的動態隨機存取記憶體
US10236040B2 (en) 2016-11-15 2019-03-19 Micron Technology, Inc. Two-step data-line precharge scheme

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212663A (en) * 1991-02-21 1993-05-18 Cypress Semiconductor Corporation Method to implement a large resettable static RAM without the large surge current
JPH07130175A (ja) 1993-09-10 1995-05-19 Toshiba Corp 半導体記憶装置
JP3544096B2 (ja) * 1997-03-26 2004-07-21 東京大学長 半導体集積回路装置
JPH1187649A (ja) * 1997-09-04 1999-03-30 Hitachi Ltd 半導体記憶装置
JPH11185467A (ja) * 1997-12-22 1999-07-09 Fujitsu Ltd 半導体集積回路装置
JPH11283369A (ja) 1998-03-27 1999-10-15 Hitachi Ltd 半導体集積回路装置
JP2001015704A (ja) * 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
JP2003132679A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP4462528B2 (ja) * 2002-06-24 2010-05-12 株式会社日立製作所 半導体集積回路装置
JP3967693B2 (ja) 2003-05-23 2007-08-29 株式会社東芝 半導体メモリ
JP4646106B2 (ja) * 2004-05-25 2011-03-09 株式会社日立製作所 半導体集積回路装置
JP2006031881A (ja) * 2004-07-20 2006-02-02 Matsushita Electric Ind Co Ltd 半導体記憶装置
US7196392B2 (en) * 2004-11-29 2007-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure for isolating integrated circuits of various operation voltages
JP5465919B2 (ja) * 2009-05-14 2014-04-09 ルネサスエレクトロニクス株式会社 半導体集積装置

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