JP2010225690A - 半導体装置および半導体基板、並びに半導体装置の製造方法 - Google Patents
半導体装置および半導体基板、並びに半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2010225690A JP2010225690A JP2009069015A JP2009069015A JP2010225690A JP 2010225690 A JP2010225690 A JP 2010225690A JP 2009069015 A JP2009069015 A JP 2009069015A JP 2009069015 A JP2009069015 A JP 2009069015A JP 2010225690 A JP2010225690 A JP 2010225690A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- protective film
- semiconductor device
- opening
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/0213—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
- H01L2224/03464—Electroless plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/03828—Applying flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0383—Reworking, e.g. shaping
- H01L2224/0384—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】半導体基板1の電極パッド2上に金属層41を形成する際、金属層41の中心部から外周部に向かって放射状に、加えてその幅を外周部に向かうほど狭くなるような溝部42を複数形成する。この金属層41に形成された溝部42をガイドとして利用することで、はんだボール6が金属層41の中心部から大きくずれて搭載された場合でも熱処理でリフローをかければ、はんだボール6を金属層41の中心部に確実にセンタリングすることが可能となる。
【選択図】図1
Description
図1(a)〜(d)は本実施形態の半導体装置を示す図である。図1(a)は金属層俯瞰図、図1(b)は図1(a)の断面線Ibにおける断面図を示したものである。図1(c)ははんだボールを搭載した金属層俯瞰図、図1(d)はリフロー後の上面図を示したものである。
図5(a)〜(b)及び図6(a)〜(b)は本実施形態の半導体装置を示す図である。図5(a)は金属層俯瞰図、図5(b)は図5(a)の断面線Vbにおける断面図を示したものである。図6(a)は第2の保護膜の俯瞰図、図6(b)は図6(a)の断面線VIbにおける断面図を示したものである。
2 電極パッド
3 保護膜
31 第1の保護膜
32 第2の保護膜
33 枝部
41 金属層
42 溝部
43 ボール保持部
5 フラックス
6 はんだボール
7 バンプ
Claims (15)
- 複数の電極パッドを備えた半導体基板と、前記半導体基板上面を覆いかつ前記電極パッドを露出するように開口部を有する保護膜と、前記開口部から露出した前記電極パッド上に形成された金属層と、前記金属層上に形成されたバンプとを備えた半導体装置であって、
前記金属層はその中心部から外周部に向かって放射状に形成された複数の溝部を備えることを特徴とする半導体装置。 - 前記金属層の溝部は前記金属層の中心部より外周部の方が細く形成されていることを特徴とする請求項1に記載の半導体装置。
- 複数の電極パッドを備えた半導体基板と、前記半導体基板上面を覆いかつ前記電極パッドを露出するように開口部を有する第1の保護膜と、前記開口部から露出した電極パッド上に形成された第2の保護膜と、前記開口部上に形成された金属層と、前記金属層上に形成されたバンプとを備えた半導体装置であって、
前記第2の保護膜は前記電極パッドの中心部から外周部に向かって放射状に形成された複数の枝部を備え、
前記金属層はその中心部から外周部に向かって放射状に形成された複数の溝部を備え、
前記金属層の溝部は前記第2の保護膜の枝部の形状に沿って形成されていることを特徴とする半導体装置。 - 前記第2の保護膜の枝部は前記電極パッドの開口部の中心部より外周部の方が細く形成されていることを特徴とする請求項3に記載の半導体装置。
- 前記第1の保護膜と前記第2の保護膜とは前記開口部端において連結していることを特徴とする請求項3または4に記載の半導体装置。
- 前記金属層において、隣接する二つの前記金属層の溝部によって区切られた部分は厚み方向に弓なりとなっていることを特徴とする請求項1から5のうちいずれか1項に記載の半導体装置。
- 複数の電極パッドと、前記電極パッドを露出するように開口部を有する保護膜と、前記開口部から露出した前記電極パッド上に形成された金属層とを備えた半導体基板であって、
前記金属層はその中心部から外周部に向かって放射状に形成された複数の溝部を備えることを特徴とする半導体基板。 - 複数の電極パッドを備えた半導体基板を有する半導体装置の製造方法であって、
前記半導体基板上面を覆うように保護膜を形成する工程と、
前記電極パッドを露出するように開口部を形成する工程と、
前記開口部から露出した前記電極パッド上に金属層を形成する工程と、
前記金属層の中心部から外周部に向かって放射状に複数の溝部を形成する工程と、
前記金属層上にバンプを形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記金属層の溝部を前記金属層の中心部より外周部の方が細くなるように形成することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記金属層を無電解めっき法で形成することを特徴とする請求項8または9に記載の半導体装置の製造方法。
- 複数の電極パッドを備えた半導体基板を有する半導体装置の製造方法であって、
前記半導体基板上面を覆うように第1の保護膜を形成する工程と、
前記電極パッドを露出するように開口部を形成する工程と、
前記開口部に前記電極パッドの中心部から外周部に向かって放射状に形成された複数の枝部を有する第2の保護膜を形成する工程と、
無電解めっき法により、前記開口部から露出した前記電極パッド上に、前記第2の保護膜の枝部の形状に沿って中心部から外周部に向かって放射状に伸びる複数の溝部を有する金属層を形成する工程と、
前記金属層上にバンプを形成する工程とを備えることを特徴とする半導体装置の製造方法。 - 前記第2の保護膜の枝部を前記電極パッドの開口部の中心部より外周部の方が細くなるように形成することを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記第1の保護膜と前記第2の保護膜とを前記開口部端において連結するように形成することを特徴とする請求項11または12に記載の半導体装置の製造方法。
- 前記第1の保護膜と前記第2の保護膜とを同じ工程で形成することを特徴とする請求項11から13のうちいずれか1項に記載の半導体装置の製造方法。
- 前記金属層において、隣接する二つの前記金属層の溝部によって区切られた部分を厚み方向に弓なりとなるように形成することを特徴とする請求項8から14のうちいずれか1項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009069015A JP5563777B2 (ja) | 2009-03-19 | 2009-03-19 | 半導体装置および半導体基板、並びに半導体装置の製造方法 |
PCT/JP2010/001137 WO2010106740A1 (ja) | 2009-03-19 | 2010-02-22 | 半導体装置および半導体基板、並びに半導体装置の製造方法 |
US13/230,395 US8525332B2 (en) | 2009-03-19 | 2011-09-12 | Semiconductor device having semiconductor substrate, and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009069015A JP5563777B2 (ja) | 2009-03-19 | 2009-03-19 | 半導体装置および半導体基板、並びに半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010225690A true JP2010225690A (ja) | 2010-10-07 |
JP5563777B2 JP5563777B2 (ja) | 2014-07-30 |
Family
ID=42739407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009069015A Expired - Fee Related JP5563777B2 (ja) | 2009-03-19 | 2009-03-19 | 半導体装置および半導体基板、並びに半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8525332B2 (ja) |
JP (1) | JP5563777B2 (ja) |
WO (1) | WO2010106740A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170097710A (ko) * | 2014-12-19 | 2017-08-28 | 마이론 워커 | 집적 회로 패키지들의 납땜성 및 자기-정렬을 개선하기 위한 스포크드 땜납 패드 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9685402B2 (en) * | 2011-12-13 | 2017-06-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming recesses in conductive layer to detect continuity for interconnect between semiconductor die and substrate |
JP6329027B2 (ja) * | 2014-08-04 | 2018-05-23 | ミネベアミツミ株式会社 | フレキシブルプリント基板 |
US20230378106A1 (en) * | 2022-05-19 | 2023-11-23 | Nxp Usa, Inc. | Patterned and planarized under-bump metallization |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0513418A (ja) * | 1991-07-04 | 1993-01-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08236583A (ja) * | 1995-02-28 | 1996-09-13 | Nec Corp | フレキシブルフィルム及び半導体装置 |
JP2000294589A (ja) * | 1999-04-06 | 2000-10-20 | Ricoh Microelectronics Co Ltd | 板状バンプ材、および、板状バンプ材形成装置 |
JP2000332016A (ja) * | 1999-05-19 | 2000-11-30 | Nec Corp | 半導体装置および半導体製造方法 |
JP2001230339A (ja) * | 2000-02-18 | 2001-08-24 | Nec Corp | 半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6387734B1 (en) * | 1999-06-11 | 2002-05-14 | Fujikura Ltd. | Semiconductor package, semiconductor device, electronic device and production method for semiconductor package |
KR20010004529A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
JP4750926B2 (ja) * | 2000-06-06 | 2011-08-17 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP2002110723A (ja) | 2000-10-02 | 2002-04-12 | Ricoh Co Ltd | ハンダボール搭載方法 |
JP2004207293A (ja) | 2002-12-24 | 2004-07-22 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US7859122B2 (en) * | 2008-04-14 | 2010-12-28 | International Business Machines Corporation | Final via structures for bond pad-solder ball interconnections |
-
2009
- 2009-03-19 JP JP2009069015A patent/JP5563777B2/ja not_active Expired - Fee Related
-
2010
- 2010-02-22 WO PCT/JP2010/001137 patent/WO2010106740A1/ja active Application Filing
-
2011
- 2011-09-12 US US13/230,395 patent/US8525332B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0513418A (ja) * | 1991-07-04 | 1993-01-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH08236583A (ja) * | 1995-02-28 | 1996-09-13 | Nec Corp | フレキシブルフィルム及び半導体装置 |
JP2000294589A (ja) * | 1999-04-06 | 2000-10-20 | Ricoh Microelectronics Co Ltd | 板状バンプ材、および、板状バンプ材形成装置 |
JP2000332016A (ja) * | 1999-05-19 | 2000-11-30 | Nec Corp | 半導体装置および半導体製造方法 |
JP2001230339A (ja) * | 2000-02-18 | 2001-08-24 | Nec Corp | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170097710A (ko) * | 2014-12-19 | 2017-08-28 | 마이론 워커 | 집적 회로 패키지들의 납땜성 및 자기-정렬을 개선하기 위한 스포크드 땜납 패드 |
KR102103628B1 (ko) | 2014-12-19 | 2020-04-23 | 마이론 워커 | 집적 회로 패키지들의 납땜성 및 자기-정렬을 개선하기 위한 스포크드 땜납 패드 |
Also Published As
Publication number | Publication date |
---|---|
US20110316154A1 (en) | 2011-12-29 |
WO2010106740A1 (ja) | 2010-09-23 |
US8525332B2 (en) | 2013-09-03 |
JP5563777B2 (ja) | 2014-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7476564B2 (en) | Flip-chip packaging process using copper pillar as bump structure | |
JP4803844B2 (ja) | 半導体パッケージ | |
KR102032172B1 (ko) | 배선 기판 및 그 제조 방법 | |
US20110285008A1 (en) | Semiconductor apparatus and semiconductor apparatus unit | |
JP2006237159A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP4601686B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2010103467A (ja) | 半導体パッケージ及びその製造方法 | |
JP5563777B2 (ja) | 半導体装置および半導体基板、並びに半導体装置の製造方法 | |
JP2006202969A (ja) | 半導体装置およびその実装体 | |
JP2013115214A (ja) | 半導体装置、半導体素子、及び半導体装置の製造方法 | |
US8697566B2 (en) | Bump structure and manufacturing method thereof | |
JP4458029B2 (ja) | 半導体装置の製造方法 | |
US9408313B2 (en) | Packaging substrate and method of fabricating the same | |
US20050017375A1 (en) | Ball grid array package substrate and method for manufacturing the same | |
JP2009283631A (ja) | 半導体装置および半導体装置の製造方法 | |
JPWO2015198838A1 (ja) | 半導体装置およびその製造方法 | |
US20220344300A1 (en) | Electronic device and manufacturing method thereof | |
JP4010311B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP4611871B2 (ja) | 半導体装置及びその製造方法、並びに電子装置 | |
JP2008198916A (ja) | 半導体装置及びその製造方法 | |
WO2011043102A1 (ja) | 回路基板 | |
JP2006073954A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2006108182A (ja) | 半導体装置およびその実装体およびその製造方法 | |
TWI473216B (zh) | 半導體製程及其半導體結構 | |
JP2011181859A (ja) | 半導体装置及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20101201 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20120208 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130514 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130702 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140401 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140409 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140507 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140514 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140603 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140613 |
|
LAPS | Cancellation because of no payment of annual fees |