JP2010206185A - 半導体デバイス、FETデバイスに非対称的なp/n接合を形成する方法及びFETデバイスを形成する方法(低電力消費のシリコン・オン・インシュレータ・デバイスのための非対称的なソース/ドレイン接合) - Google Patents
半導体デバイス、FETデバイスに非対称的なp/n接合を形成する方法及びFETデバイスを形成する方法(低電力消費のシリコン・オン・インシュレータ・デバイスのための非対称的なソース/ドレイン接合) Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000000034 method Methods 0.000 title claims description 21
- 239000012212 insulator Substances 0.000 title abstract description 8
- 239000000463 material Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 210000000746 body region Anatomy 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
【解決手段】 半導体デバイスは、バルク基板上に形成された埋め込み絶縁層と、埋め込み絶縁層上に形成され電界効果トランジスタ(FET)のボディ領域に対応する第1の型の半導体材料と、ボディ領域の互いに対向する側部に隣接するように埋め込み絶縁層の上方に設けられFETデバイスのソース領域及びドレイン領域に対応し且つ第1の型の半導体材料のバンドギャップと異なるバンドギャップを有する第2の型の半導体材料とを有し、FETのソース側のp/n接合の大部分は第1の型の半導体材料及び第2の型の半導体材料のうち狭いバンドギャップを有する半導体材料内に配置され、且つFETのドレイン側のp/n接合は、第1の型の半導体材料及び第2の型の半導体材料のうち広いバンドギャップを有する半導体材料内に配置される。
【選択図】 図5
Description
104 埋め込み絶縁層
106 半導体層
108 浅いトレンチ分離領域
110 ゲート導体
112 ゲート絶縁層
114 第1組の側壁スペーサ
116 浅いソース/ドレイン延長領域
118 第2組の側壁スペーサ
119 凹部
120 埋め込みシリコン・ゲルマニウム領域
122、124 P+/N接合
Claims (12)
- バルク基板上に形成された埋め込み絶縁層と、
前記埋め込み絶縁層上に形成されかつ電界効果トランジスタ(FET)デバイスのボディ領域に対応する第1の型の半導体材料と、
前記ボディ領域の互いに対向する側部に隣接するように前記埋め込み絶縁層の上方に設けられFETデバイスのソース領域及びドレイン領域に対応し且つ前記第1の型の半導体材料のバンドギャップと異なるバンドギャップを有する第2の型の半導体材料とを備え、
前記FETデバイスの前記ソース領域側のp/n接合は前記第1の型の半導体材料及び前記第2の型の半導体材料のうち狭いバンドギャップを有する半導体材料内に配置され、前記FETデバイスの前記ドレイン領域側のp/n接合は、前記第1の型の半導体材料及び前記第2の型の半導体材料のうち広いバンドギャップを有する半導体材料内に配置されている、半導体デバイス。 - 前記第1の型の半導体材料のバンドギャップが、前記第2の型の半導体材料のバンドギャップより広い、請求項1に記載の半導体デバイス。
- 前記第1の型の半導体材料がシリコンであり、前記第2の型の半導体材料がシリコン・ゲルマニウムである、請求項2に記載の半導体デバイス。
- 前記第2の型の半導体材料のバンドギャップが、前記第1の型の半導体材料のバンドギャップより広い、請求項1に記載の半導体デバイス。
- 前記FETデバイスがPFETである、請求項1に記載の半導体デバイス。
- 電界効果トランジスタ(FET)デバイスに非対称的なp/n接合を形成する方法であって、
バルク基板上に形成された埋め込み絶縁層と、前記埋め込み絶縁層上に形成されFETデバイスのボディ領域に対応する第1の型の半導体材料と、前記ボディ領域の互いに対向する側部に隣接するように前記埋め込み絶縁層の上方に設けられ前記FETデバイスのソース領域及びドレイン領域に対応し且つ前記第1の型の半導体材料のバンドギャップと異なるバンドギャップを有する第2の型の半導体材料とを有するFETデバイスに対して、角度を付けられた方向でドーパントの注入を行うステップを含み、
前記FETデバイスの前記ソース領域側のp/n接合が前記第1の型の半導体材料及び前記第2の型の半導体材料のうち狭いバンドギャップを有する半導体材料内に配置され、前記FETデバイスの前記ドレイン領域側のp/n接合が前記第1の型の半導体材料及び前記第2の型の半導体材料のうち広いバンドギャップを有する半導体材料内に配置される、方法。 - 前記第1の型の半導体材料のバンドギャップが、前記第2の型の半導体材料のバンドギャップより広い、請求項6に記載の方法。
- 前記第1の型の半導体材料がシリコンであり、前記第2の型の半導体材料がシリコン・ゲルマニウムである、請求項7に記載の方法。
- 前記第2の型の半導体材料のバンドギャップが、前記第1の型の半導体材料のバンドギャップよりも広い、請求項6に記載の方法。
- 前記FETデバイスがPFETである、請求項6に記載の方法。
- 電界効果トランジスタ(FET)デバイスを形成する方法であって、
バルク基板上に埋め込み絶縁層を形成するステップと、
前記埋め込み絶縁層上に第1の型の半導体材料を形成するステップと、
前記第1の型の半導体材料のうちFETデバイスのソース領域及びドレイン領域に対応する部分を除去し、前記第1の型の半導体材料のうち前記FETデバイスのボディ領域に対応する部分を残すステップと、
前記FETデバイスのソース領域及びドレイン領域に対応し且つ前記第1の型の半導体材料のバンドギャップと異なるバンドギャップを有する第2の型の半導体材料を前記埋め込み絶縁層の上方に形成するステップと、
前記FETデバイスの前記ソース領域側のp/n接合の大部分が前記第1の型の半導体材料及び前記第2の型の半導体材料のうち狭いバンドギャップを有する半導体材料内に配置され、前記FETデバイスの前記ドレイン領域側のp/n接合が前記第1の型の半導体材料及び前記第2の型の半導体材料のうち広いバンドギャップを有する半導体材料内に配置されるように、角度を付けられた方向でドーパントの注入を行うステップとを含む、方法。 - 垂直な方向で前記ドーパントの注入を行うステップを含む、請求項11に記載の方法。
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US8928047B2 (en) | 2010-11-03 | 2015-01-06 | Texas Instruments Incorporated | MOSFET with source side only stress |
US9768254B2 (en) | 2015-07-30 | 2017-09-19 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
US9870953B2 (en) | 2015-10-26 | 2018-01-16 | International Business Machines Corporation | System on chip material co-integration |
FR3078440B1 (fr) * | 2018-02-23 | 2022-06-24 | St Microelectronics Crolles 2 Sas | Jonction pn |
US11393713B2 (en) | 2019-04-23 | 2022-07-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method therefore |
US11557650B2 (en) | 2019-04-23 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US11233140B2 (en) | 2019-04-23 | 2022-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
KR102411803B1 (ko) * | 2019-04-23 | 2022-06-22 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 반도체 디바이스 및 그 제조 방법 |
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