JP2010153860A - 半導体構造体および半導体構造体を形成する方法 - Google Patents
半導体構造体および半導体構造体を形成する方法 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
【解決手段】SOI基板の最上部半導体層の一部分にパターン形成して、実質的に垂直な側壁を有する半導体フィン18が作成される。半導体フィンのボディ領域20とは反対の導電型のドーピングを有する2つのソース領域62間の半導体フィンの上面で半導体フィンのボディ領域の一部分が露出される。2つのソース領域と、2つのソース領域間の露出されたボディ領域の上面のすぐ上に、金属半導体合金部分82が形成される。ボディ領域への低抵抗接触を可能にするために、イオン注入によってボディ領域の露出された最上部部分のドーピング濃度を高めることができるか、または高密度の結晶欠陥を有する再結合領域を形成することができる。
【選択図】図7F
Description
18 半導体フィン
20 ボディ領域
30 誘電体フィン・キャップ部分
64 ドレイン領域
84 ドレイン側金属半導体合金部分
90 ミドル・オブ・ライン(MOL)誘電体層
94 ドレイン側コンタクト・ビア
Claims (21)
- 第1の側壁と第2の側壁と実質的に水平な上面とを有し、基板上に位置する絶縁体層のすぐ上に位置する半導体フィンであって、前記第1および第2の側壁が実質的に相互に平行であり、実質的に垂直である前記半導体フィンと、
前記半導体フィン内に位置し、第1の導電型のドーピングを有し、前記絶縁体層に垂直に接するボディ領域と、
前記半導体フィンの第1の端部内で前記第1の側壁のすぐ上に位置し、第2の導電型のドーピングを有する第1のソース領域であって、前記第2の導電型が前記第1の導電型の反対である第1のソース領域と、
前記半導体フィンの前記第1の端部内で前記第2の側壁のすぐ上に位置し、前記第2の導電型のドーピングを有する第2のソース領域と、
前記第1のソース領域、前記第2のソース領域、および前記第1の導電型のドーピングを有し、前記第1のソース領域と前記第2のソース領域との間に位置する前記半導体フィンの一部分の上面に接する金属半導体合金部分と、
を含む、半導体構造体。 - 前記半導体フィンの第2の端部内に位置し、前記第2の導電型のドーピングを有するドレイン領域をさらに含み、前記ドレイン領域が前記ボディ領域によって前記第1および第2のソース領域から分離され、前記第2の端部が前記半導体フィンの前記第1の端部の反対側に位置する、請求項1記載の半導体構造体。
- 前記ドレイン領域が、前記第1の側壁のすぐ上ならびに前記第2の側壁のすぐ上に位置する、請求項2記載の半導体構造体。
- 前記ドレイン領域が、連続したものであり、前記半導体フィンの端壁のすぐ上に位置する一部分を含み、前記端壁が、前記第1の側壁および前記第2の側壁に実質的に垂直であり、前記第1の側壁および前記第2の側壁に直接隣接する、請求項3記載の半導体構造体。
- 前記第1の側壁の中央部分に接する第1のゲート誘電体と、
前記第2の側壁の中央部分に接する第2のゲート誘電体と、
前記第1のゲート誘電体および前記第2のゲート誘電体に接するゲート導体と、
をさらに含む、請求項3記載の半導体構造体。 - 前記第1のゲート誘電体が前記第2のゲート誘電体に接しない、請求項5記載の半導体構造体。
- 前記第1のソース領域のエッジと前記第2のソース領域のエッジが前記ゲート導体のエッジに実質的に位置合わせされ、前記ドレイン領域のエッジが前記ゲート導体の他のエッジに実質的に位置合わせされる、請求項3記載の半導体構造体。
- 前記ボディ領域および前記ドレイン領域に垂直に接する誘電体フィン・キャップ部分をさらに含む、請求項3記載の半導体構造体。
- 前記誘電体フィン・キャップ部分が前記ドレイン領域全体の上に重なり、前記誘電体フィン・キャップ部分のエッジが前記ゲート導体に実質的に位置合わせされる、請求項8記載の半導体構造体。
- 前記ボディ領域に垂直に接する誘電体フィン・キャップ部分と、
前記誘電体フィン・キャップ部分に垂直に接するゲート導体であって、前記ゲート導体の側壁が前記誘電体フィン・キャップ部分の側壁と実質的に垂直に一致するゲート導体と、
をさらに含む、請求項3記載の半導体構造体。 - 前記ドレイン領域が、連続したものであり、前記半導体フィンの上面のすぐ上に位置し、前記半導体フィンの端壁から前記誘電体フィン・キャップ部分のエッジまで延びる一部分を含む、請求項10記載の半導体構造体。
- 前記ボディ領域の一部分が前記ドレイン領域の一部分の下になる、請求項11記載の半導体構造体。
- 前記ボディ領域と前記ドレイン領域との境界が前記半導体部分の上面から前記絶縁体層まで延び、前記境界全体が前記ゲート導体のエッジと実質的に垂直に一致する、請求項11記載の半導体構造体。
- 前記第1の導電型のドーピングを有する前記半導体フィンの前記一部分が前記ボディ領域の一部分である、請求項1記載の半導体構造体。
- 前記半導体フィンの前記一部分が、前記ボディ領域のドーパント濃度より高いドーパント濃度を有する第1の導電型のドープ領域である、請求項1記載の半導体構造体。
- 前記第1のソース領域および前記第2のソース領域のドーパント濃度が前記第1の導電型のドープ領域の前記ドーパント濃度より高い、請求項15記載の半導体構造体。
- 前記半導体フィン全体が単一結晶性である、請求項1記載の半導体構造体。
- 半導体構造体を形成する方法であって、
第1の側壁と第2の側壁と実質的に水平な上面とを有し、絶縁体層のすぐ上に位置し、第1の導電型のドーピングを有する半導体フィンを形成することであって、前記第1および第2の側壁が実質的に相互に平行であり、実質的に垂直であることと、
前記半導体フィンの第1の端部内で前記第1の側壁のすぐ上に第2の導電型のドーピングを有する第1のソース領域を形成することであって、前記第2の導電型が前記第1の導電型の反対であることと、
前記半導体フィンの前記第1の端部内で前記第2の側壁のすぐ上に前記第2の導電型のドーピングを有する第2のソース領域を形成することと、
前記第1のソース領域、前記第2のソース領域、および前記第1の導電型のドーピングを有し、前記第1のソース領域と前記第2のソース領域との間に位置する前記半導体フィンの一部分の上面のすぐ上に金属半導体合金部分を形成することと、
を含む、方法。 - 前記半導体フィンの第2の端部内に前記第2の導電型のドーピングを有するドレイン領域を形成することをさらに含み、前記ドレイン領域が前記第1および第2のソース領域に接せず、前記第2の端部が前記第1の端部の反対側に位置する、請求項18記載の方法。
- 前記絶縁体層と最上部半導体層とを含むセミコンダクタ・オン・インシュレータ(SOI)層を提供することと、
前記最上部半導体層上に誘電体フィン・キャップ層を形成することと、
前記誘電体フィン・キャップ層および前記最上部半導体層にパターン形成することであって、前記誘電体フィン・キャップ層の残りの部分が誘電体フィン・キャップ部分を構成し、前記最上部半導体層の残りの部分が前記半導体フィンを構成し、前記第1の側壁および前記第2の側壁が前記誘電体フィン・キャップ部分の側壁と実質的に垂直に一致することと、
をさらに含む、請求項19記載の方法。 - 半導体構造体を形成する方法であって、
第1の側壁と第2の側壁と実質的に水平な上面とを有し、絶縁体層のすぐ上に位置し、第1の導電型のドーピングを有する半導体フィンを形成することであって、前記第1および第2の側壁が実質的に相互に平行であり、実質的に垂直であることと、
前記実質的に水平な上面のすぐ下に、アモルファス化した半導体材料を含み、前記第1の導電型のドーピングを有する再結合中心含有半導体領域を形成することと、
前記再結合中心含有半導体領域および前記半導体フィン内に形成された少なくとも1つのソース領域のすぐ上に、第2の導電型のドーピングを有する金属半導体合金部分を形成することであって、前記第2の導電型が前記第1の導電型の反対であることと、
を含む、方法。
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