JP2010045762A - 半導体集積回路及びその制御方法 - Google Patents

半導体集積回路及びその制御方法 Download PDF

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Publication number
JP2010045762A
JP2010045762A JP2009080450A JP2009080450A JP2010045762A JP 2010045762 A JP2010045762 A JP 2010045762A JP 2009080450 A JP2009080450 A JP 2009080450A JP 2009080450 A JP2009080450 A JP 2009080450A JP 2010045762 A JP2010045762 A JP 2010045762A
Authority
JP
Japan
Prior art keywords
clock
signal
enable signal
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009080450A
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English (en)
Japanese (ja)
Other versions
JP2010045762A5 (enExample
Inventor
Gyeong-Nam Kim
京 男 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JP2010045762A publication Critical patent/JP2010045762A/ja
Publication of JP2010045762A5 publication Critical patent/JP2010045762A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2009080450A 2008-08-08 2009-03-27 半導体集積回路及びその制御方法 Pending JP2010045762A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080077701A KR100940849B1 (ko) 2008-08-08 2008-08-08 반도체 집적 회로 및 그 제어 방법

Publications (2)

Publication Number Publication Date
JP2010045762A true JP2010045762A (ja) 2010-02-25
JP2010045762A5 JP2010045762A5 (enExample) 2012-07-12

Family

ID=41652335

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009080450A Pending JP2010045762A (ja) 2008-08-08 2009-03-27 半導体集積回路及びその制御方法

Country Status (3)

Country Link
US (1) US7808290B2 (enExample)
JP (1) JP2010045762A (enExample)
KR (1) KR100940849B1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100930416B1 (ko) * 2008-08-11 2009-12-08 주식회사 하이닉스반도체 반도체 집적 회로 및 그 제어 방법
US8934317B2 (en) 2012-01-13 2015-01-13 Samsung Electronics Co., Ltd. Semiconductor memory devices having internal clock signals and memory systems including such memory devices
TWI456906B (zh) * 2012-03-27 2014-10-11 Novatek Microelectronics Corp 頻率合成器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250382A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd クロック再生回路
JP2002093167A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
JP2006277870A (ja) * 2005-03-30 2006-10-12 Elpida Memory Inc 半導体記憶装置
JP2007221750A (ja) * 2006-02-16 2007-08-30 Hynix Semiconductor Inc パワーダウンモードの間、周期的にロッキング動作を実行する機能を有するｄｌｌ及びそのロッキング動作方法
JP2007531404A (ja) * 2004-03-22 2007-11-01 モビウス マイクロシステムズ，インク． モノリシックなクロック・ジェネレータおよびタイミング／周波数リファレンス

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422572B1 (ko) 2001-06-30 2004-03-12 주식회사 하이닉스반도체 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자
KR100528788B1 (ko) * 2003-06-27 2005-11-15 주식회사 하이닉스반도체 지연 고정 루프 및 그 구동 방법
KR100808052B1 (ko) * 2005-09-28 2008-03-07 주식회사 하이닉스반도체 반도체 메모리 장치
KR100733465B1 (ko) * 2005-09-29 2007-06-29 주식회사 하이닉스반도체 지연고정루프회로
US7676686B2 (en) * 2005-09-29 2010-03-09 Hynix Semiconductor, Inc. Delay locked loop circuit and synchronous memory device including the same
US7489172B2 (en) 2005-09-29 2009-02-10 Hynix Semiconductor Inc. DLL driver control circuit
KR100753137B1 (ko) * 2005-09-29 2007-08-30 주식회사 하이닉스반도체 지연고정루프 및 지연고정루프 클럭 생성방법
KR100753101B1 (ko) * 2005-09-29 2007-08-29 주식회사 하이닉스반도체 락킹 페일 방지 위한 지연고정루프 클럭 생성 방법 및 장치
KR100784907B1 (ko) * 2006-06-30 2007-12-11 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
KR100810072B1 (ko) * 2006-09-29 2008-03-05 주식회사 하이닉스반도체 지연고정루프를 구비하는 반도체 메모리 장치 및 그의 구동방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001250382A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd クロック再生回路
JP2002093167A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
JP2007531404A (ja) * 2004-03-22 2007-11-01 モビウス マイクロシステムズ，インク． モノリシックなクロック・ジェネレータおよびタイミング／周波数リファレンス
JP2006277870A (ja) * 2005-03-30 2006-10-12 Elpida Memory Inc 半導体記憶装置
JP2007221750A (ja) * 2006-02-16 2007-08-30 Hynix Semiconductor Inc パワーダウンモードの間、周期的にロッキング動作を実行する機能を有するｄｌｌ及びそのロッキング動作方法

Also Published As

Publication number Publication date
US7808290B2 (en) 2010-10-05
US20100033219A1 (en) 2010-02-11
KR100940849B1 (ko) 2010-02-09

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