JP2010021534A - 配線基板及びその作製方法、並びに半導体装置及びその作製方法 - Google Patents
配線基板及びその作製方法、並びに半導体装置及びその作製方法 Download PDFInfo
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- JP2010021534A JP2010021534A JP2009134374A JP2009134374A JP2010021534A JP 2010021534 A JP2010021534 A JP 2010021534A JP 2009134374 A JP2009134374 A JP 2009134374A JP 2009134374 A JP2009134374 A JP 2009134374A JP 2010021534 A JP2010021534 A JP 2010021534A
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29499—Shape or distribution of the fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
-
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- H01—ELECTRIC ELEMENTS
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Abstract
【解決手段】シート状繊維体の両面に、該シート状繊維体の内部まで含浸した絶縁性樹脂層と、前記絶縁性樹脂層に囲まれる領域に設けられた貫通配線を有し、前記貫通配線は、前記シート状繊維体を挟んで前記絶縁性樹脂層の両面に導電性材料が露出し、該導電性材料は、前記シート状繊維体の内部まで含浸している配線基板及びその作製方法、並びに、さらに、絶縁層の表面にバンプが露出した集積回路チップとを有し、前記バンプが前記貫通配線と接触するように、前記集積回路チップが前記樹脂含浸繊維体複合基板に密接している半導体装置及びその作製方法に関する。
【選択図】図2
Description
本実施の形態では、配線基板の構成とその作製方法について、図1(A)及び図1(B)、図2(A)〜図2(D)、を用いて説明する。
本実施の形態では、貫通配線が設けられた樹脂含浸繊維体複合基板を用いた半導体装置の構成と、その作製方法について、図3(A)〜図3(D)、図4(A)〜図4(E)、図5(A)〜図5(D)、図7(A)〜図7(B)を用いて説明する。
52a 薄膜トランジスタ
52b 薄膜トランジスタ
53a 不純物領域
53b 不純物領域
54 ゲート絶縁層
55a ゲート電極
55b ゲート電極
56 絶縁層
57a 配線
57b 配線
58a 配線
58b 配線
61 素子層
62 記憶素子
63a チャネル形成領域
63b チャネル形成領域
64 トンネル酸化層
65 絶縁膜
66 絶縁膜
67 絶縁膜
71 素子層
72 フォトダイオード
73 受光部
74 電極
81 素子層
83 アンテナ
84 電極
91 チャネル形成領域
92 不純物領域
93 フローティングゲート
94 コントロール絶縁層
95 コントロールゲート
97 配線
98 配線
101 導電性樹脂
102 配線
103 領域
111 基板
112 剥離層
113 繊維体
113a 経糸
113b 緯糸
113c バスケットホール
114 絶縁性樹脂
120 構造体
120a 構造体
120b 構造体
122 レーザビーム
123 溝
Claims (4)
- シート状繊維体の両面に、該シート状繊維体の内部まで含浸した絶縁性樹脂層と、
前記絶縁性樹脂層に囲まれる領域に設けられた貫通配線を有し、
前記貫通配線は、前記シート状繊維体を挟んで前記絶縁性樹脂層の両面に導電性材料が露出し、該導電性材料は、前記シート状繊維体の内部まで含浸していることを特徴とする配線基板。 - シート状繊維体の一部の領域に、導電性樹脂を含浸させて貫通配線を形成し、
前記シート状繊維体の前記導電性樹脂が含浸していない領域に、絶縁性樹脂層を含浸させることを特徴とする配線基板の作製方法。 - シート状繊維体の両面に、該シート状繊維体の内部まで含浸した絶縁性樹脂層と、前記絶縁性樹脂層に囲まれる領域に、前記シート状繊維体に含浸し前記絶縁性樹脂層の両面に導電性材料が露出する貫通配線を有する樹脂含浸繊維体複合基板と、
絶縁層の表面にバンプが露出した集積回路チップとを有し、
前記バンプが前記貫通配線と接触するように、前記集積回路チップが前記樹脂含浸繊維体複合基板に密接していることを特徴とする半導体装置。 - 絶縁層の表面にバンプが露出した集積回路チップを形成し、
シート状繊維体の一部の領域に、前記バンプと接触するように、導電性樹脂を含浸させて貫通配線を形成し、
前記シート状繊維体の前記導電性樹脂が含浸していない領域に、絶縁性樹脂層を含浸させることを特徴とする半導体装置の作製方法。
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JPS60200590A (ja) * | 1984-03-24 | 1985-10-11 | ダイソー株式会社 | 印刷回路基板及びその製法 |
JP2001024081A (ja) * | 1999-07-08 | 2001-01-26 | Toshiba Corp | 導電基体及びその製造方法 |
Cited By (5)
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JP2010141294A (ja) * | 2008-11-11 | 2010-06-24 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
WO2016017553A1 (ja) * | 2014-07-28 | 2016-02-04 | 東邦テナックス株式会社 | プリプレグおよび繊維強化複合材料 |
JP5898391B1 (ja) * | 2014-07-28 | 2016-04-06 | 東邦テナックス株式会社 | プリプレグおよび繊維強化複合材料 |
JP2016183328A (ja) * | 2014-07-28 | 2016-10-20 | 東邦テナックス株式会社 | プリプレグおよび繊維強化複合材料 |
US10544274B2 (en) | 2014-07-28 | 2020-01-28 | Toho Tenax Co., Ltd. | Prepreg and fiber-reinforced composite material |
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JP5639749B2 (ja) | 2014-12-10 |
US20090302457A1 (en) | 2009-12-10 |
US8044499B2 (en) | 2011-10-25 |
KR20090128336A (ko) | 2009-12-15 |
KR101594316B1 (ko) | 2016-02-16 |
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