JP2009543267A5 - - Google Patents

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Publication number
JP2009543267A5
JP2009543267A5 JP2009518412A JP2009518412A JP2009543267A5 JP 2009543267 A5 JP2009543267 A5 JP 2009543267A5 JP 2009518412 A JP2009518412 A JP 2009518412A JP 2009518412 A JP2009518412 A JP 2009518412A JP 2009543267 A5 JP2009543267 A5 JP 2009543267A5
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JP
Japan
Prior art keywords
power supply
supply voltage
memory cells
node
coupled
Prior art date
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Granted
Application number
JP2009518412A
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English (en)
Japanese (ja)
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JP5164276B2 (ja
JP2009543267A (ja
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Publication date
Priority claimed from US11/427,610 external-priority patent/US7292495B1/en
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Publication of JP2009543267A publication Critical patent/JP2009543267A/ja
Publication of JP2009543267A5 publication Critical patent/JP2009543267A5/ja
Application granted granted Critical
Publication of JP5164276B2 publication Critical patent/JP5164276B2/ja
Active legal-status Critical Current
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JP2009518412A 2006-06-29 2007-04-19 低電圧で読出／書込動作を行うメモリを有する集積回路 Active JP5164276B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/427,610 2006-06-29
US11/427,610 US7292495B1 (en) 2006-06-29 2006-06-29 Integrated circuit having a memory with low voltage read/write operation
PCT/US2007/066908 WO2008002713A2 (en) 2006-06-29 2007-04-19 Integrated circuit having a memory with low voltage read/write operation

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012274485A Division JP5598876B2 (ja) 2006-06-29 2012-12-17 低電圧で読出／書込動作を行うメモリを有する集積回路

Publications (3)

Publication Number Publication Date
JP2009543267A JP2009543267A (ja) 2009-12-03
JP2009543267A5 true JP2009543267A5 (enExample) 2010-06-03
JP5164276B2 JP5164276B2 (ja) 2013-03-21

Family

ID=38653441

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2009518412A Active JP5164276B2 (ja) 2006-06-29 2007-04-19 低電圧で読出／書込動作を行うメモリを有する集積回路
JP2012274485A Active JP5598876B2 (ja) 2006-06-29 2012-12-17 低電圧で読出／書込動作を行うメモリを有する集積回路

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012274485A Active JP5598876B2 (ja) 2006-06-29 2012-12-17 低電圧で読出／書込動作を行うメモリを有する集積回路

Country Status (5)

Country Link
US (2) US7292495B1 (enExample)
JP (2) JP5164276B2 (enExample)
CN (2) CN101479803B (enExample)
TW (1) TW200809870A (enExample)
WO (1) WO2008002713A2 (enExample)

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US9940996B1 (en) * 2017-03-01 2018-04-10 Nxp Usa, Inc. Memory circuit having increased write margin and method therefor
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US11069424B2 (en) * 2018-11-07 2021-07-20 Arm Limited Sensor for performance variation of memory read and write characteristics
US11488658B2 (en) 2020-04-29 2022-11-01 Qualcomm Incorporated Write assist scheme with bitline
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US20230013651A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory cell power supply

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