CN101479803B - 包括具有低电压读/写操作的存储器的集成电路 - Google Patents

包括具有低电压读/写操作的存储器的集成电路 Download PDF

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Publication number
CN101479803B
CN101479803B CN200780024544XA CN200780024544A CN101479803B CN 101479803 B CN101479803 B CN 101479803B CN 200780024544X A CN200780024544X A CN 200780024544XA CN 200780024544 A CN200780024544 A CN 200780024544A CN 101479803 B CN101479803 B CN 101479803B
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China
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voltage
memory cells
supply voltage
coupled
terminal
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CN200780024544XA
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Chinese (zh)
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CN101479803A (zh
Inventor
普拉桑特·U·肯卡雷
安德鲁·C·拉塞尔
大卫·R·彼阿登
詹姆斯·D·伯内特
特洛伊·L·库柏
张沙彦
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN101479803A publication Critical patent/CN101479803A/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
CN200780024544XA 2006-06-29 2007-04-19 包括具有低电压读/写操作的存储器的集成电路 Active CN101479803B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/427,610 2006-06-29
US11/427,610 US7292495B1 (en) 2006-06-29 2006-06-29 Integrated circuit having a memory with low voltage read/write operation
PCT/US2007/066908 WO2008002713A2 (en) 2006-06-29 2007-04-19 Integrated circuit having a memory with low voltage read/write operation

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201110328909.6A Division CN102394100B (zh) 2006-06-29 2007-04-19 包括具有低电压读/写操作的存储器的集成电路

Publications (2)

Publication Number Publication Date
CN101479803A CN101479803A (zh) 2009-07-08
CN101479803B true CN101479803B (zh) 2012-07-18

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CN200780024544XA Active CN101479803B (zh) 2006-06-29 2007-04-19 包括具有低电压读/写操作的存储器的集成电路
CN201110328909.6A Active CN102394100B (zh) 2006-06-29 2007-04-19 包括具有低电压读/写操作的存储器的集成电路

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CN201110328909.6A Active CN102394100B (zh) 2006-06-29 2007-04-19 包括具有低电压读/写操作的存储器的集成电路

Country Status (5)

Country Link
US (2) US7292495B1 (enExample)
JP (2) JP5164276B2 (enExample)
CN (2) CN101479803B (enExample)
TW (1) TW200809870A (enExample)
WO (1) WO2008002713A2 (enExample)

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US7903483B2 (en) * 2008-11-21 2011-03-08 Freescale Semiconductor, Inc. Integrated circuit having memory with configurable read/write operations and method therefor
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US20100283445A1 (en) * 2009-02-18 2010-11-11 Freescale Semiconductor, Inc. Integrated circuit having low power mode voltage regulator
US8319548B2 (en) * 2009-02-18 2012-11-27 Freescale Semiconductor, Inc. Integrated circuit having low power mode voltage regulator
US7864617B2 (en) * 2009-02-19 2011-01-04 Freescale Semiconductor, Inc. Memory with reduced power supply voltage for a write operation
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US8315117B2 (en) * 2009-03-31 2012-11-20 Freescale Semiconductor, Inc. Integrated circuit memory having assisted access and method therefor
US8379466B2 (en) 2009-03-31 2013-02-19 Freescale Semiconductor, Inc. Integrated circuit having an embedded memory and method for testing the memory
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US8634263B2 (en) * 2009-04-30 2014-01-21 Freescale Semiconductor, Inc. Integrated circuit having memory repair information storage and method therefor
US8059482B2 (en) * 2009-06-19 2011-11-15 Freescale Semiconductor, Inc. Memory using multiple supply voltages
US8045402B2 (en) * 2009-06-29 2011-10-25 Arm Limited Assisting write operations to data storage cells
US8400819B2 (en) * 2010-02-26 2013-03-19 Freescale Semiconductor, Inc. Integrated circuit having variable memory array power supply voltage
US9875788B2 (en) * 2010-03-25 2018-01-23 Qualcomm Incorporated Low-power 5T SRAM with improved stability and reduced bitcell size
US8514611B2 (en) * 2010-08-04 2013-08-20 Freescale Semiconductor, Inc. Memory with low voltage mode operation
US8345469B2 (en) 2010-09-16 2013-01-01 Freescale Semiconductor, Inc. Static random access memory (SRAM) having bit cells accessible by separate read and write paths
US20120119824A1 (en) * 2010-11-16 2012-05-17 Texas Instruments Incorporated Bias voltage source
US9035629B2 (en) 2011-04-29 2015-05-19 Freescale Semiconductor, Inc. Voltage regulator with different inverting gain stages
US9299395B2 (en) * 2012-03-26 2016-03-29 Intel Corporation Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
US9460778B2 (en) * 2013-08-15 2016-10-04 Samsung Electronics Co., Ltd. Static random access memory with bitline boost
US9286971B1 (en) * 2014-09-10 2016-03-15 Apple Inc. Method and circuits for low latency initialization of static random access memory
US9990022B2 (en) 2016-06-30 2018-06-05 Qualcomm Incorporated Adaptive power multiplexing with a power distribution network
US9940996B1 (en) * 2017-03-01 2018-04-10 Nxp Usa, Inc. Memory circuit having increased write margin and method therefor
US9934846B1 (en) 2017-03-01 2018-04-03 Nxp Usa, Inc. Memory circuit and method for increased write margin
US10691195B2 (en) * 2018-02-28 2020-06-23 Qualcomm Incorporated Selective coupling of memory to voltage rails based on operating mode of processor
US11069424B2 (en) * 2018-11-07 2021-07-20 Arm Limited Sensor for performance variation of memory read and write characteristics
US11488658B2 (en) 2020-04-29 2022-11-01 Qualcomm Incorporated Write assist scheme with bitline
TWI768939B (zh) * 2021-05-31 2022-06-21 力晶積成電子製造股份有限公司 記憶體裝置
US12354644B2 (en) * 2021-07-09 2025-07-08 Stmicroelectronics International N.V. Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)
US20230013651A1 (en) * 2021-07-16 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. Static random access memory cell power supply

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US6552357B2 (en) * 1998-02-27 2003-04-22 Kabushiki Kaisha Toshiba Semiconductor memory device having plate lines and precharge circuits

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Also Published As

Publication number Publication date
JP2013054818A (ja) 2013-03-21
US20080019206A1 (en) 2008-01-24
JP5164276B2 (ja) 2013-03-21
CN102394100A (zh) 2012-03-28
TW200809870A (en) 2008-02-16
CN102394100B (zh) 2014-09-24
WO2008002713A3 (en) 2008-06-19
CN101479803A (zh) 2009-07-08
WO2008002713A2 (en) 2008-01-03
US7292495B1 (en) 2007-11-06
JP5598876B2 (ja) 2014-10-01
US7542369B2 (en) 2009-06-02
JP2009543267A (ja) 2009-12-03

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