JP2009538534A - 高効率両面冷却ディスクリートパワーパッケージ、特に革新的なパワーモジュール用の基本素子 - Google Patents
高効率両面冷却ディスクリートパワーパッケージ、特に革新的なパワーモジュール用の基本素子 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 56
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Abstract
【選択図】 図13
Description
a)機械的特性の向上
i)応力が低減された両面冷却半導体ダイ
ii)半導体ダイに適合した熱膨張係数を有する材料の選択
iii)適合した熱膨張係数による信頼性の向上
iv)直接冷却液と接触しており、過酷な環境で使用可能な気密封止された頑丈なパッケージ
b)電気的特性及び熱的特性の向上
i)半導体デバイスのすべてのパッドに広いはんだ付け接触面積を用いることによる共通パッケージ全体の低インダクタンス
ii)二面冷却すると共にはんだダイ取付け及び広い接触面績を用いた、低電気抵抗及び低熱抵抗による電流/電力能力の向上
iii)半導体ダイの両面における電気絶縁性
iv)利用可能なパッケージ空間の最適な使用及びそれによる最適な電力密度
c)製造特性及び操作特性の向上
i)事前に組み立てられた部品パッケージは、容易な操作及び容易なパワーモジュールへの集積に適している。
d)下記による低い製造コスト及び低い試験コスト
i)特定用途向けにカスタマイズせず、大量生産が可能であり、カスタマイズは末端消費者によってなされ、末端消費者は、カスタマイズした回路又はパワーモジュールにデバイスを組み合わせることができる。
iii)DBCカードをディスクリートパッケージされた素子に分離する前に、電気的/パラメトリック最終試験をDBCカードレベルで行える。
iv)ディスクリート標準パッケージと同様に、完成したパッケージを試験し、認定することができ、これによって標準認定プロセス後に製品がリリースされる。
e)特有の消費者の利点
i)部品パッケージは最新のパワー基板の熱膨張係数に適合し、そのため多様な用途に魅力的である。
ii)用途が柔軟な組立て部品は、末端消費者において、基本的な「組立てキット」としてパッケージを用いて、特定用途向け回路に容易に組み合わせ可能である。
iii)より高価なDBC基板と主なパッケージの外形及び実装面積を用途とは独立させたままでの、カスタマイズされる外部リード及び外部端子の様々な可能性による用途の柔軟性
iv)DBCのセラミックの種類(たとえば、Al2O3セラミック、AlNセラミック、SiNセラミック、及び他のセラミック)を、用途の要件に合わせることによるコスト効率の良い材料の選択
f)選択的機能の容易な実施
i)パッケージは、ヒートシンク又はパワーモジュール基板への高効率で革新的な省スペースの垂直集積を可能にする基本素子である。
ii)パッケージのHV絶縁により、両面冷却及び均一な直接液体冷却が実施可能であり、最大限の電力及びパッケージ密度が提供される。
iii)パッケージのDBC素子の露出したCu層を、接地されたEMI遮蔽として用いることによって、追加のEMI遮蔽機能が実施され得る。
iv)HV絶縁パッケージ、たとえば露出したCuパッド上に取り付けられたゲート−ドライバ又はセンサなどの「スマート部品」の容易な集積
Claims (20)
- 互いに対向する第1の表面及び第2の表面のそれぞれに設けられた第1の電源電極及び第2の電源電極を有する第1の半導体ダイと、
互いに絶縁されている第1の表面及び第2の表面のそれぞれに設けられた第1の導電層及び第2の導電層をそれぞれが有する第1の絶縁板及び第2の各絶縁板であり、前記半導体ダイの前記第1の電源電極及び前記第2の電源電極が前記第1の絶縁板及び前記第2の絶縁板それぞれの前記第1の導電層に電気的且つ機械的に固定されて、前記第1の絶縁板及び前記第2の絶縁板が、これらの絶縁板間に前記半導体ダイを挟んだサンドイッチ構造体を成している、第1の絶縁板及び第2の絶縁板と、
前記第2の絶縁板の前記第1の表面上にある少なくとも第1のリード導電体及び第2のリード導電体であり、前記サンドイッチ構造体内で前記第1の電源電極及び前記第2の電源電極のそれぞれに電気的に接続されており、前記サンドイッチ構造体の周縁部を越えて延びている、第1のド導電体及び第2のリード導電体と
を備え、前記第2の導電層が前記表面の外側にあり、前記半導体ダイを冷却するために双方とも露出している、薄い平坦な半導体パッケージ。 - 前記第1の絶縁板及び前記第2の絶縁板が熱伝導性セラミックである、請求項1に記載の半導体パッケージ。
- 前記半導体ダイがその第1の表面上に導電性制御電極を有し、前記第2の絶縁板の前記第1の表面上の第3のリード導電体が前記制御電極に接続しており、前記第1のリード導電体及び前記第2のリード導電体と同程度延びている、請求項1に記載の半導体パッケージ。
- 前記半導体ダイはMOSゲートデバイスである、請求項3に記載の半導体パッケージ。
- 前記第1の絶縁板の前記第1の導電層が、前記半導体ダイを受ける平坦な中央部と、一段高い周縁領域とを有し、前記第2の電源電極が、前記第1の導電層の前記一段高い周縁領域上の導電性表面に接続している、請求項1に記載の半導体パッケージ。
- 前記シリコンダイが第1の表面上に導電性制御電極を有し、前記第2の絶縁板の前記第1の表面上の前記第3のリード導電体が、前記制御電極に接続しており、前記第1のリード導電体及び前記第2のリード導電体と同程度延びており、前記第2の絶縁板上の前記第1の導電層の前記パターンが前記制御電極の形状に合致したさらなるパターンを有する、請求項6に記載の半導体パッケージ。
- 前記パッケージが約4mm未満の厚さを有する、請求項1に記載の半導体パッケージ。
- 前記パッケージが約4mm未満の厚さを有する、請求項5に記載の半導体パッケージ。
- 前記パッケージが約4mm未満の厚さを有する、請求項7に記載の半導体パッケージ。
- 前記第1及び第2の絶縁板、並びに前記第1及び第2の絶縁板の導電層がDBC基板内に形成されている、請求項1に記載の半導体デバイス。
- 前記第1及び第2の絶縁板、並びに前記第1及び第2の絶縁板の導電層がDBC基板内に形成されている、請求項7に記載の半導体デバイス。
- 当該半導体パッケージパッケージの周囲に巻かれて押し付けられ、前記第1の絶縁板及び前記第2の絶縁板上の前記第2の電極と良好な熱伝達をし、前記電源電極及び前記リード導電体から間隔を空けて配置され、絶縁されている、U字型の金属製装着クリップをさらに含む、請求項1に記載の半導体パッケージ。
- 前記パッケージの周囲に巻かれて押し付けられ、前記第1及び第2の絶縁板上の前記第2の電極と良好な熱伝達をし、前記電源電極及び前記リード導電体から間隔を空けて配置され、絶縁されている、U字型の金属製装着クリップをさらに含む、請求項8に記載の半導体パッケージ。
- 前記パッケージの周囲に巻かれて押し付けられ、前記第1及び第2の絶縁板上の前記第2の電極と良好な熱伝達をし、前記電源電極及び前記リード導電体から間隔を空けて配置され、絶縁されている、U字型の金属製装着クリップをさらに含む、請求項10に記載の半導体パッケージ。
- 両面冷却されることが可能な半導体パッケージであって、
第1のパターニングされた第1のDBCウエハ及び第2のDBCウエハと、
第1の電源電極及び第2の電源電極を有する少なくとも1つの半導体ダイと
を備え、
前記第1のDBCウエハ及び前記第2のDBCウエハの各々が、薄くて電気的に導電性であり、且つ電気的に絶縁性である板の両面に第1の導電層及び第2の導電層を有し、前記第1の導電層が、中央の平坦な領域から延びる周縁縁部を有し、前記半導体ダイの前記第2の電源電極が、前記第1のDBC層の前記第1の導電層の前記中央の平坦な領域に接続しており、前記第2のDBCウエハの前記第1の導電層が、前記第1の電源電極のパターンと、前記第1のDBCウエハの前記第1の導電層の前記周縁縁部とに合致したパターンを有し、前記第1のDBCウエハが前記第2のDBCウエハに、双方のDBCウエハの間に前記半導体ウエハをサンドイッチする形で固定され、前記第1のDBCウエハの前記第1の導電層の前記第1の電源電極及び前記縁部が前記第2のDBCウエハの前記第1の導電層の前記パターン上の各領域と電気的に接触しており、リード導電体が、前記第2のDBCウエハの前記第1の導電層の前記パターンに接続し、前記サンドイッチ構造体の周縁部を越えて延びている、半導体パッケージ。 - 前記シリコンダイがその第1の表面上に導電性制御電極を有し、前記第2の絶縁板の前記第1の表面上の第3のリード導電体が前記制御電極に接続しており、前記第1のリード導電体及び前記第2のリード導電体と同程度延びている、請求項16に記載のパッケージ。
- 前記ダイがMOSゲートデバイスである、請求項17に記載のパッケージ。
- 前記パッケージが約4mm未満の厚さを有する、請求項16に記載のパッケージ。
- 前記第1の半導体ダイと横方向に間隔を空けて配置され、両面それぞれに第1の電源電極及び第2の電源電極を有する第2の半導体ダイを含み、
前記第1の絶縁板及び前記第2の絶縁板上の前記第1の導電層が、前記第2の半導体ダイの前記第1の電源電極及び前記第2の電源電極に接触するための導電パターン部を有する、請求項1に記載のデバイス。 - 前記第1の半導体及び前記第2の半導体ダイが、それぞれ、MOSゲートデバイス及び並列接続のダイオードである、請求項20に記載のデバイス。
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PCT/US2007/012328 WO2007139852A2 (en) | 2006-05-23 | 2007-05-23 | Highly efficient both-side-cooled discrete power package, especially basic element for innovative power modules |
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US7619302B2 (en) | 2009-11-17 |
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WO2007139852A3 (en) | 2008-05-02 |
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