JP2009523312A - デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法 - Google Patents

デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法 Download PDF

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Publication number
JP2009523312A
JP2009523312A JP2008530164A JP2008530164A JP2009523312A JP 2009523312 A JP2009523312 A JP 2009523312A JP 2008530164 A JP2008530164 A JP 2008530164A JP 2008530164 A JP2008530164 A JP 2008530164A JP 2009523312 A JP2009523312 A JP 2009523312A
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Japan
Prior art keywords
layer
substrate
pattern
template
metal
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Pending
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JP2008530164A
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English (en)
Japanese (ja)
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JP2009523312A5 (enExample
Inventor
マクダナルド，スーズン，エス
Original Assignee
トッパン、フォウタマスクス、インク
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Application filed by トッパン、フォウタマスクス、インク filed Critical トッパン、フォウタマスクス、インク
Publication of JP2009523312A publication Critical patent/JP2009523312A/ja
Publication of JP2009523312A5 publication Critical patent/JP2009523312A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2008530164A 2005-09-07 2006-09-06 デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法 Pending JP2009523312A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71462705P 2005-09-07 2005-09-07
PCT/US2006/034697 WO2007030527A2 (en) 2005-09-07 2006-09-06 Photomask for the fabrication of a dual damascene structure and method for forming the same

Publications (2)

Publication Number Publication Date
JP2009523312A true JP2009523312A (ja) 2009-06-18
JP2009523312A5 JP2009523312A5 (enExample) 2009-10-15

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ID=37836413

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JP2008530164A Pending JP2009523312A (ja) 2005-09-07 2006-09-06 デュアル・ダマシン構造を製造するためのフォトマスクおよびその形成方法

Country Status (3)

Country Link
JP (1) JP2009523312A (enExample)
CN (1) CN101505974A (enExample)
WO (1) WO2007030527A2 (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118081A (ja) * 2005-12-07 2008-05-22 Canon Inc 半導体装置の製造方法と物品の製造方法
JP2009543334A (ja) * 2006-06-30 2009-12-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 位置合せおよびフィーチャの成形に対してフレキシビリティが向上したナノインプリント技術
JP2011249648A (ja) * 2010-05-28 2011-12-08 Toshiba Corp パターン形成方法
JP2012223909A (ja) * 2011-04-15 2012-11-15 Fujikura Ltd インプリントモールドの製造方法及びインプリントモールド
JP2014187573A (ja) * 2013-03-25 2014-10-02 Kyocera Crystal Device Corp 圧電素子ウエハ形成方法
KR20180037764A (ko) * 2016-10-05 2018-04-13 삼성전자주식회사 반도체 소자 제조방법
US12204251B2 (en) 2021-03-23 2025-01-21 Kioxia Corporation Pattern generation method, template, and method for manufacturing template

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2942739B1 (fr) * 2009-03-03 2011-05-13 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
FR2942738B1 (fr) 2009-03-03 2016-04-15 Commissariat Energie Atomique Procede de fabrication d'un moule pour la lithographie par nano-impression
KR101711646B1 (ko) 2009-12-11 2017-03-03 엘지디스플레이 주식회사 임프린트용 몰드의 제조방법 및 임프린트용 몰드를 이용한 패턴 형성방법
US9034233B2 (en) 2010-11-30 2015-05-19 Infineon Technologies Ag Method of processing a substrate
CN102650822B (zh) * 2011-02-24 2015-03-11 中芯国际集成电路制造(上海)有限公司 双重图形化的纳米压印模具及其形成方法
KR102710915B1 (ko) * 2016-10-25 2024-09-26 엘지디스플레이 주식회사 임프린트 몰드 및 이의 제조방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954420A (ja) * 1995-08-11 1997-02-25 Dainippon Printing Co Ltd 多段エッチング型基板の製造方法
WO2003107094A1 (en) * 2002-06-18 2003-12-24 Motorola, Inc. Multi-tiered lithographic template
JP2004071587A (ja) * 2002-08-01 2004-03-04 Hitachi Ltd スタンパとスタンパを用いたパターン転写方法及び転写パターンによる構造体の形成方法
WO2004102624A2 (en) * 2003-05-08 2004-11-25 Freescale Semiconductor, Inc. Unitary dual damascene process using imprint lithography
WO2004114382A1 (ja) * 2003-06-20 2004-12-29 Matsushita Electric Industrial Co. Ltd. パターン形成方法及び半導体装置の製造方法
WO2005031855A1 (en) * 2003-09-29 2005-04-07 International Business Machines Corporation Fabrication method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7037639B2 (en) * 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US7083880B2 (en) * 2002-08-15 2006-08-01 Freescale Semiconductor, Inc. Lithographic template and method of formation and use

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954420A (ja) * 1995-08-11 1997-02-25 Dainippon Printing Co Ltd 多段エッチング型基板の製造方法
WO2003107094A1 (en) * 2002-06-18 2003-12-24 Motorola, Inc. Multi-tiered lithographic template
JP2004071587A (ja) * 2002-08-01 2004-03-04 Hitachi Ltd スタンパとスタンパを用いたパターン転写方法及び転写パターンによる構造体の形成方法
WO2004102624A2 (en) * 2003-05-08 2004-11-25 Freescale Semiconductor, Inc. Unitary dual damascene process using imprint lithography
WO2004114382A1 (ja) * 2003-06-20 2004-12-29 Matsushita Electric Industrial Co. Ltd. パターン形成方法及び半導体装置の製造方法
WO2005031855A1 (en) * 2003-09-29 2005-04-07 International Business Machines Corporation Fabrication method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118081A (ja) * 2005-12-07 2008-05-22 Canon Inc 半導体装置の製造方法と物品の製造方法
JP2009543334A (ja) * 2006-06-30 2009-12-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 位置合せおよびフィーチャの成形に対してフレキシビリティが向上したナノインプリント技術
JP2011249648A (ja) * 2010-05-28 2011-12-08 Toshiba Corp パターン形成方法
JP2012223909A (ja) * 2011-04-15 2012-11-15 Fujikura Ltd インプリントモールドの製造方法及びインプリントモールド
JP2014187573A (ja) * 2013-03-25 2014-10-02 Kyocera Crystal Device Corp 圧電素子ウエハ形成方法
KR20180037764A (ko) * 2016-10-05 2018-04-13 삼성전자주식회사 반도체 소자 제조방법
KR102614850B1 (ko) 2016-10-05 2023-12-18 삼성전자주식회사 반도체 소자 제조방법
US12204251B2 (en) 2021-03-23 2025-01-21 Kioxia Corporation Pattern generation method, template, and method for manufacturing template

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Publication number Publication date
WO2007030527A2 (en) 2007-03-15
WO2007030527A3 (en) 2009-04-30
CN101505974A (zh) 2009-08-12

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