JP2009239262A5 - - Google Patents

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Publication number
JP2009239262A5
JP2009239262A5 JP2009039615A JP2009039615A JP2009239262A5 JP 2009239262 A5 JP2009239262 A5 JP 2009239262A5 JP 2009039615 A JP2009039615 A JP 2009039615A JP 2009039615 A JP2009039615 A JP 2009039615A JP 2009239262 A5 JP2009239262 A5 JP 2009239262A5
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JP
Japan
Prior art keywords
substrate
manufacturing
composite
tray
stage
Prior art date
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Application number
JP2009039615A
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English (en)
Japanese (ja)
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JP2009239262A (ja
JP5409041B2 (ja
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Priority to JP2009039615A priority Critical patent/JP5409041B2/ja
Priority claimed from JP2009039615A external-priority patent/JP5409041B2/ja
Publication of JP2009239262A publication Critical patent/JP2009239262A/ja
Publication of JP2009239262A5 publication Critical patent/JP2009239262A5/ja
Application granted granted Critical
Publication of JP5409041B2 publication Critical patent/JP5409041B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009039615A 2008-03-07 2009-02-23 複合基板の製造装置及び当該複合基板の製造装置を用いた複合基板の製造方法 Expired - Fee Related JP5409041B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009039615A JP5409041B2 (ja) 2008-03-07 2009-02-23 複合基板の製造装置及び当該複合基板の製造装置を用いた複合基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008058222 2008-03-07
JP2008058222 2008-03-07
JP2009039615A JP5409041B2 (ja) 2008-03-07 2009-02-23 複合基板の製造装置及び当該複合基板の製造装置を用いた複合基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009239262A JP2009239262A (ja) 2009-10-15
JP2009239262A5 true JP2009239262A5 (enExample) 2012-03-29
JP5409041B2 JP5409041B2 (ja) 2014-02-05

Family

ID=41052389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009039615A Expired - Fee Related JP5409041B2 (ja) 2008-03-07 2009-02-23 複合基板の製造装置及び当該複合基板の製造装置を用いた複合基板の製造方法

Country Status (3)

Country Link
US (1) US20090223628A1 (enExample)
JP (1) JP5409041B2 (enExample)
KR (1) KR20090096353A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005517B (zh) * 2009-08-26 2013-09-18 首尔Opto仪器股份有限公司 利用激光剥离技术制造发光二极管的方法和激光剥离装置
CN104247000A (zh) * 2011-12-28 2014-12-24 Ev集团E·索尔纳有限责任公司 衬底的粘合方法和装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342090A (en) * 1980-06-27 1982-07-27 International Business Machines Corp. Batch chip placement system
US4857689A (en) * 1988-03-23 1989-08-15 High Temperature Engineering Corporation Rapid thermal furnace for semiconductor processing
JPH0410631A (ja) * 1990-04-27 1992-01-14 Mitsubishi Electric Corp 半導体チップ吸着治具
US6468923B1 (en) * 1999-03-26 2002-10-22 Canon Kabushiki Kaisha Method of producing semiconductor member
JP4103391B2 (ja) * 1999-10-14 2008-06-18 信越半導体株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US6474477B1 (en) * 2001-05-02 2002-11-05 Ching T. Chang Carrier assembly for semiconductor IC (integrated circuit) packages
JP2004055860A (ja) * 2002-07-22 2004-02-19 Renesas Technology Corp 半導体装置の製造方法
KR100476591B1 (ko) * 2002-08-26 2005-03-18 삼성전자주식회사 웨이퍼 테이블과, 이를 이용한 웨이퍼 쏘잉/소자 접착장치와, 웨이퍼 쏘잉/소자 분류 장치
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
US6974168B2 (en) * 2002-09-30 2005-12-13 Intel Corporation System and method for performing simultaneous precision die bond of photonic components onto a single substrate
US20080190981A1 (en) * 2003-12-04 2008-08-14 Yasutomo Okajima Method for Processing Substrate, Apparatus for Processing Substrate, Method for Conveying Substrate and Mechanism for Conveying Substrate
JP4299721B2 (ja) * 2003-12-09 2009-07-22 株式会社ルネサステクノロジ 半導体装置の搬送方法および半導体装置の製造方法
JP4677717B2 (ja) * 2004-01-19 2011-04-27 株式会社Sumco Ｓｏｉウェーハの製造方法およびその装置
JP2006210898A (ja) * 2004-12-28 2006-08-10 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウェーハ
WO2007014320A2 (en) * 2005-07-27 2007-02-01 Silicon Genesis Corporation Method and structure for fabricating multiple tile regions onto a plate using a controlled cleaving process
JP4595740B2 (ja) * 2005-08-16 2010-12-08 パナソニック株式会社 チップ反転装置およびチップ反転方法ならびにチップ搭載装置
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
TWI322476B (en) * 2006-10-05 2010-03-21 Advanced Semiconductor Eng Die bonder and die bonding method thereof
US8387674B2 (en) * 2007-11-30 2013-03-05 Taiwan Semiconductor Manufacturing Comany, Ltd. Chip on wafer bonder

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