JP2009194072A5 - - Google Patents

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Publication number
JP2009194072A5
JP2009194072A5 JP2008031811A JP2008031811A JP2009194072A5 JP 2009194072 A5 JP2009194072 A5 JP 2009194072A5 JP 2008031811 A JP2008031811 A JP 2008031811A JP 2008031811 A JP2008031811 A JP 2008031811A JP 2009194072 A5 JP2009194072 A5 JP 2009194072A5
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JP
Japan
Prior art keywords
film
dielectric constant
sod
low dielectric
msq
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2008031811A
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English (en)
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JP2009194072A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2008031811A priority Critical patent/JP2009194072A/ja
Priority claimed from JP2008031811A external-priority patent/JP2009194072A/ja
Priority to TW098100865A priority patent/TW200949931A/zh
Priority to US12/370,055 priority patent/US7795142B2/en
Publication of JP2009194072A publication Critical patent/JP2009194072A/ja
Publication of JP2009194072A5 publication Critical patent/JP2009194072A5/ja
Abandoned legal-status Critical Current

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Description

また、ここでは、ＣＶＤ法でＳｉＯＣ膜を形成しているが、形成方法はこれに限るものではない。例えば、ポロジェン材料を含有する溶液をスピンコートし熱処理して薄膜を形成するＳＯＤ（ｓｐｉｎ ｏｎ ｄｉｅｌｅｃｔｒｉｃ ｃｏａｔｉｎｇ）法を用いても好適である。ＳＯＤ法で形成する低誘電率絶縁膜の材料としては、例えば、メチルシロセスキオキサン（ｍｅｔｈｙｌ ｓｉｌｓｅｓｑｕｉｏｘａｎｅ：ＭＳＱ）を用いることができる。また、ＭＳＱの他に、例えば、ポリメチルシロキサン、ポリシロキサン、ハイドロジェンシロセスキオキサンなどのシロキサン骨格を有する膜、および多孔質シリカ膜などのポーラス膜からなる群から選択される少なくとも一種を用いて形成しても構わない。ＳＯＤ法では、例えば、スピナーで成膜し、このウエハをホットプレート上で窒素雰囲気中でのベークを行なうことでポロジェン材料２２２が均一に含有された例えば有機シロキサンを主骨格成分とするＳｉＯＣ膜２２０を形成することができる。いずれの低誘電率絶縁膜の材料を用いても、最終的に比誘電率が２．５未満の低誘電率を得ることができる。
JP2008031811A 2008-02-13 2008-02-13 半導体装置の製造方法 Abandoned JP2009194072A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008031811A JP2009194072A (ja) 2008-02-13 2008-02-13 半導体装置の製造方法
TW098100865A TW200949931A (en) 2008-02-13 2009-01-10 Method for fabricating a semiconductor device
US12/370,055 US7795142B2 (en) 2008-02-13 2009-02-12 Method for fabricating a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008031811A JP2009194072A (ja) 2008-02-13 2008-02-13 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2009194072A JP2009194072A (ja) 2009-08-27
JP2009194072A5 true JP2009194072A5 (ja) 2010-04-08

Family

ID=40939243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008031811A Abandoned JP2009194072A (ja) 2008-02-13 2008-02-13 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US7795142B2 (ja)
JP (1) JP2009194072A (ja)
TW (1) TW200949931A (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090116477A (ko) * 2008-05-07 2009-11-11 삼성전자주식회사 초저유전막을 포함하는 반도체 소자의 제조 방법
US20110232677A1 (en) * 2010-03-29 2011-09-29 Tokyo Electron Limited Method for cleaning low-k dielectrics
JP5636277B2 (ja) * 2010-12-27 2014-12-03 富士フイルム株式会社 多孔質絶縁膜及びその製造方法
JP5985406B2 (ja) * 2013-01-31 2016-09-06 株式会社東芝 半導体装置の製造方法及び半導体装置の製造装置
US9165822B2 (en) * 2013-03-11 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of forming same
KR101998788B1 (ko) 2013-04-22 2019-07-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9054052B2 (en) * 2013-05-28 2015-06-09 Global Foundries Inc. Methods for integration of pore stuffing material
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
CN104617036B (zh) * 2015-01-14 2018-07-27 华天科技（昆山）电子有限公司 晶圆级芯片尺寸封装中通孔互连的制作方法
KR102460075B1 (ko) * 2016-01-27 2022-10-31 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9859154B2 (en) * 2016-03-11 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of interconnect structure of semiconductor device
KR102616489B1 (ko) 2016-10-11 2023-12-20 삼성전자주식회사 반도체 장치 제조 방법
US10950426B2 (en) 2018-08-14 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric layer, interconnection structure using the same, and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US6964919B2 (en) * 2002-08-12 2005-11-15 Intel Corporation Low-k dielectric film with good mechanical strength
JP2004274020A (ja) 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
US7125793B2 (en) * 2003-12-23 2006-10-24 Intel Corporation Method for forming an opening for an interconnect structure in a dielectric layer having a photosensitive material
US7557035B1 (en) * 2004-04-06 2009-07-07 Advanced Micro Devices, Inc. Method of forming semiconductor devices by microwave curing of low-k dielectric films
US7585722B2 (en) * 2006-01-10 2009-09-08 International Business Machines Corporation Integrated circuit comb capacitor
US20070232046A1 (en) 2006-03-31 2007-10-04 Koji Miyata Damascene interconnection having porous low K layer with improved mechanical properties
JP4419025B2 (ja) 2006-09-04 2010-02-24 ソニー株式会社 半導体装置の製造方法
US7723226B2 (en) * 2007-01-17 2010-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
WO2008094792A1 (en) * 2007-01-29 2008-08-07 Applied Materials, Inc. Novel air gap integration scheme

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