JP2009158942A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2009158942A JP2009158942A JP2008305824A JP2008305824A JP2009158942A JP 2009158942 A JP2009158942 A JP 2009158942A JP 2008305824 A JP2008305824 A JP 2008305824A JP 2008305824 A JP2008305824 A JP 2008305824A JP 2009158942 A JP2009158942 A JP 2009158942A
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Images
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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Abstract
【解決手段】絶縁体でなる基板上の第1の絶縁層と、第1の絶縁層上に形成された第1の配線層と、第1の絶縁層上の第1の配線層が形成された領域以外の領域に形成された第2の絶縁層と、第1の配線層及び第2の絶縁層上に形成され、チャネル形成領域と不純物領域を有する単結晶半導体層と、単結晶半導体層のチャネル形成領域上にゲート絶縁層を介して形成されたゲート電極と、第1の配線層、第2の絶縁層、単結晶半導体層及びゲート電極を覆うように形成された第3の絶縁層と、第3の絶縁層上に形成された第2の配線層とを設け、第1の配線層と単結晶半導体層の不純物領域が接続し、第1の配線層と第2の配線層が電気的に接続する。
【選択図】図1
Description
本実施の形態では、半導体装置の製造方法の一例について、図1乃至5を参照して説明する。より具体的には、図1を用いてSOI基板の製造方法について説明し、図2乃至図4を用いて半導体装置の製造方法について説明し、図5を用いて上記SOI基板に用いる基板の加工方法について説明する。
・加速電圧 10kV以上100kV以下(好ましくは30kV以上80kV以下)
・ドーズ量 1×1016/cm2以上4×1016/cm2以下
・ビーム電流密度 2μA/cm2以上(好ましくは5μA/cm2以上、より好ましくは10μA/cm2以上)
本実施の形態では、単結晶半導体基板の加工方法の別の一例について説明する。なお、本実施の形態における単結晶半導体基板の加工方法は、実施の形態1において図5を参照して説明した単結晶半導体基板の加工方法と共通する部分が多い。このため、本実施の形態においては、実施の形態1と相違する部分についてのみ説明することとする。
本実施の形態では、上記実施の形態と異なる半導体装置及びその作製方法に関して図7を参照して説明する。
本実施の形態では、上記実施の形態と異なる半導体装置及びその作製方法に関して図8を参照して説明する。
本実施の形態では、半導体装置のうち、特に表示装置を用いた電子機器について、図9及び10を参照して説明する。
本実施の形態では、耐圧を考慮したトランジスタの構成について図11と図12を用いて説明する。はじめに、図1、5、6などに示す方法を用いてSOI基板を作製する(図11(A)参照)。該SOI基板は、ベース基板100上に絶縁層126、絶縁層124、絶縁層122及び配線層118、単結晶半導体層132を順に積層した構造を有している。なお、本実施の形態においては、配線層118を部分的に設ける構成としたが、開示する発明はこれに限られず、絶縁層124上の全面に配線層118を有する構成としても良い。本実施の形態に示すトランジスタにおいて、配線層118はドレイン配線(又はソース配線)として機能する。
110 単結晶半導体基板
112 絶縁層
114 損傷領域
116 導電層
118 配線層
118a 配線層
118b 配線層
118c 第1の電極
120 絶縁層
122 絶縁層
124 絶縁層
126 絶縁層
128 単結晶半導体層
130 単結晶半導体基板
132 単結晶半導体層
134 領域
136 領域
140 イオンビーム
142 レーザー光
200 単結晶半導体層
202 単結晶半導体層
204 ゲート絶縁層
206 ゲート電極
208 ゲート電極
209 電極
210 不純物領域
211 容量素子
212 不純物領域
214 サイドウォール
216 サイドウォール
218 高濃度不純物領域
220 低濃度不純物領域
222 チャネル形成領域
224 高濃度不純物領域
226 低濃度不純物領域
228 チャネル形成領域
230 絶縁層
232 配線層
234 配線層
240 領域
242 領域
250 nチャネル型トランジスタ
252 pチャネル型トランジスタ
260 半導体層
262 半導体層
264 p型領域
266 n型領域
268 ゲート絶縁層
270 ゲート電極
272 絶縁層
274 配線層
901 筺体
902 支持台
903 表示部
904 スピーカー部
905 ビデオ入力端子
911 本体
912 表示部
913 受像部
914 操作キー
915 外部接続ポート
916 シャッターボタン
921 本体
922 筐体
923 表示部
924 キーボード
925 外部接続ポート
926 ポインティングデバイス
931 本体
932 表示部
933 スイッチ
934 操作キー
935 赤外線ポート
941 本体
942 筐体
943 表示部
944 表示部
945 部
946 操作キー
947 スピーカー部
951 本体
952 表示部
953 操作キー
961 本体
962 表示部
963 筐体
964 外部接続ポート
965 リモコン受信部
966 受像部
967 バッテリー
968 音声入力部
969 操作キー
971 本体
972 筐体
973 表示部
974 音声入力部
975 音声出力部
976 操作キー
977 外部接続ポート
978 アンテナ
1000 携帯電子機器
1001 筐体
1002 筐体
1011 表示部
1012 スピーカー
1013 マイクロフォン
1014 操作キー
1015 ポインティングデバイス
1016 カメラ用レンズ
1017 外部接続端子
1021 キーボード
1022 外部メモリスロット
1023 カメラ用レンズ
1024 ライト
1025 イヤフォン端子
Claims (8)
- 絶縁体でなる基板上の第1の絶縁層と、
前記第1の絶縁層上に選択的に形成された第1の配線層と、
前記第1の絶縁層上の、前記第1の配線層が形成された領域以外の領域に形成された第2の絶縁層と、
前記第1の配線層及び前記第2の絶縁層上に形成され、チャネル形成領域と不純物領域を有する単結晶半導体層と、
前記単結晶半導体層のチャネル形成領域上にゲート絶縁層を介して形成されたゲート電極と、
前記第1の配線層、前記第2の絶縁層、前記単結晶半導体層及び前記ゲート電極を覆うように形成された第3の絶縁層と、
前記第3の絶縁層上に形成された第2の配線層と、を有し、
前記第1の配線層と前記単結晶半導体層の不純物領域が電気的に接続されており、
前記第1の配線層と前記第2の配線層が電気的に接続されていることを特徴とする半導体装置。 - 絶縁体でなる基板上の第1の絶縁層と、
前記第1の絶縁層上に選択的に形成された第1の配線層及び第1の電極と、
前記第1の絶縁層上の、前記第1の配線層及び前記第1の電極が形成された領域以外の領域に形成された第2の絶縁層と、
前記第1の配線層及び前記第2の絶縁層上に形成され、チャネル形成領域と不純物領域を有する単結晶半導体層と、
前記単結晶半導体層のチャネル形成領域上にゲート絶縁層を介して形成されたゲート電極と、
前記第1の電極上に前記ゲート絶縁層を介して形成された第2の電極と、
前記第1の配線層、前記第2の絶縁層、前記単結晶半導体層、前記第1の電極及び前記第2の電極ゲート電極を覆うように形成された第3の絶縁層と、
前記第3の絶縁層上に設けられた第2の配線層と、を有し、
前記第1の配線層と前記単結晶半導体層の不純物領域が電気的に接続されており、
前記第1の配線層と前記第2の配線層が電気的に接続されていることを特徴とする半導体装置。 - 請求項1又は請求項2において、
前記第2の配線層は、前記第3の絶縁層に接して形成され、前記第3の絶縁層に設けられた開口部において、前記単結晶半導体層と異なる単結晶半導体層の不純物領域に電気的に接続されていることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1の絶縁層は、酸化珪素、窒化珪素、酸化窒化珪素、窒化酸化珪素のいずれかを含む層の積層構造を有することを特徴とする半導体装置。 - 単結晶半導体基板にイオンを照射することにより、該単結晶半導体基板に損傷領域を形成し、
前記単結晶半導体基板の表面に選択的に第1の配線層を形成し、
前記単結晶半導体基板の表面の、前記第1の配線層が形成された領域以外の領域に第1の絶縁層を形成し、
前記第1の配線層及び前記第1の絶縁層と接するように第2の絶縁層を形成し、
前記第2の絶縁層の表面を、絶縁体でなる基板の表面と接触させることにより、前記第2の絶縁層と前記絶縁体でなる基板を接合させ、
前記単結晶半導体基板を前記損傷領域にて分離させることにより、前記絶縁体でなる基板の表面に前記第1の配線層と単結晶半導体層との積層体を形成し、
前記単結晶半導体層をパターニングすることにより、前記第1の配線層の一部を露出させた後、ゲート絶縁層、ゲート電極、第3の絶縁層を順に形成し、
前記第3の絶縁層に開口部を形成することにより前記第1の配線層の一部を露出させ、
前記第3の絶縁層上に、前記第1の配線層と電気的に接続する第2の配線層を形成することを特徴とする半導体装置の作製方法。 - 単結晶半導体基板にイオンを照射することにより、該単結晶半導体基板に損傷領域を形成し、
前記単結晶半導体基板の表面に選択的に第1の配線層及び第1の電極を形成し、
前記単結晶半導体基板の表面の、前記第1の配線層及び前記第1の電極が形成された領域以外の領域に第1の絶縁層を形成し、
前記第1の配線層、前記第1の電極及び前記第1の絶縁層と接するように第2の絶縁層を形成し、
前記第2の絶縁層の表面を、絶縁体でなる基板の表面と接触させることにより、前記第2の絶縁層と前記絶縁体でなる基板を接合させ、
前記単結晶半導体基板を前記損傷領域にて分離させることにより、前記絶縁体でなる基板の表面に前記第1の配線層及び前記第1の電極と単結晶半導体層との積層体を形成し、
前記単結晶半導体層をパターニングすることにより、前記第1の配線層の一部と前記第1の電極を露出させ、
パターニングされた前記単結晶半導体層、露出した前記第1の配線層の一部及び前記第1の電極上にゲート絶縁層を形成し、
前記単結晶半導体層上に前記ゲート絶縁層を介してゲート電極を形成し、
前記第1の電極上に前記ゲート絶縁層を介して第2の電極を形成し、
前記単結晶半導体層、前記第1の配線層及び前記第2の電極を覆うように第3の絶縁層を形成し、
前記第3の絶縁層に開口部を形成することにより前記第1の配線層の一部を露出させ、
前記第3の絶縁層上に、前記第1の配線層と電気的に接続する第2の配線層を形成することを特徴とする半導体装置の作製方法。 - 請求項5又は請求項6において、
前記絶縁体でなる基板の表面に形成された前記単結晶半導体層のパターニング前に、前記単結晶半導体層にレーザー光を照射することを特徴とする半導体装置の作製方法。 - 請求項5乃至請求項7のいずれか一において、
前記第1の配線層を形成する前に、前記単結晶半導体基板に対してしきい値電圧を制御するための不純物を選択的に添加することを特徴とする半導体装置の作製方法。
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US (1) | US8304832B2 (ja) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013077817A (ja) * | 2011-09-16 | 2013-04-25 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2013077815A (ja) * | 2011-09-16 | 2013-04-25 | Semiconductor Energy Lab Co Ltd | 半導体装置および半導体装置の作製方法 |
JP2015213185A (ja) * | 2009-12-18 | 2015-11-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
KR20200026836A (ko) * | 2017-07-14 | 2020-03-11 | 썬에디슨 세미컨덕터 리미티드 | 반도체 온 절연체 구조의 제조 방법 |
Families Citing this family (9)
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JP2009158853A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体装置 |
US8513090B2 (en) * | 2009-07-16 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate, and semiconductor device |
TWI512997B (zh) | 2009-09-24 | 2015-12-11 | Semiconductor Energy Lab | 半導體裝置,電源電路,和半導體裝置的製造方法 |
CN102576737B (zh) | 2009-10-09 | 2015-10-21 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
EP2497115A4 (en) | 2009-11-06 | 2015-09-02 | Semiconductor Energy Lab | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR |
CN105609509A (zh) | 2009-12-04 | 2016-05-25 | 株式会社半导体能源研究所 | 显示装置 |
TWI787452B (zh) * | 2011-01-26 | 2022-12-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
DE102014205130A1 (de) | 2014-03-19 | 2015-09-24 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Speicherzelle |
CN114609843A (zh) * | 2022-03-07 | 2022-06-10 | 江西晶浩光学有限公司 | 一种可变光圈、摄像模组及电子设备 |
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- 2008-12-01 JP JP2008305824A patent/JP5433220B2/ja not_active Expired - Fee Related
- 2008-12-01 US US12/325,729 patent/US8304832B2/en not_active Expired - Fee Related
- 2008-12-02 EP EP08020904.2A patent/EP2068366A3/en not_active Withdrawn
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JP2015213185A (ja) * | 2009-12-18 | 2015-11-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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JP2013077815A (ja) * | 2011-09-16 | 2013-04-25 | Semiconductor Energy Lab Co Ltd | 半導体装置および半導体装置の作製方法 |
KR20200026836A (ko) * | 2017-07-14 | 2020-03-11 | 썬에디슨 세미컨덕터 리미티드 | 반도체 온 절연체 구조의 제조 방법 |
KR102390772B1 (ko) | 2017-07-14 | 2022-04-25 | 썬에디슨 세미컨덕터 리미티드 | 반도체 온 절연체 구조의 제조 방법 |
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KR101594335B1 (ko) | 2016-02-16 |
EP2068366A2 (en) | 2009-06-10 |
US20090140337A1 (en) | 2009-06-04 |
KR20090057903A (ko) | 2009-06-08 |
JP5433220B2 (ja) | 2014-03-05 |
US8304832B2 (en) | 2012-11-06 |
EP2068366A3 (en) | 2015-07-01 |
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