JP2009099792A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2009099792A5 JP2009099792A5 JP2007270259A JP2007270259A JP2009099792A5 JP 2009099792 A5 JP2009099792 A5 JP 2009099792A5 JP 2007270259 A JP2007270259 A JP 2007270259A JP 2007270259 A JP2007270259 A JP 2007270259A JP 2009099792 A5 JP2009099792 A5 JP 2009099792A5
- Authority
- JP
- Japan
- Prior art keywords
- film
- processed
- leaving
- films
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 9
- 238000004519 manufacturing process Methods 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007270259A JP4976977B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
| US12/251,791 US7732338B2 (en) | 2007-10-17 | 2008-10-15 | Method of fabricating semiconductor device with reduced pitch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007270259A JP4976977B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009099792A JP2009099792A (ja) | 2009-05-07 |
| JP2009099792A5 true JP2009099792A5 (enExample) | 2010-04-08 |
| JP4976977B2 JP4976977B2 (ja) | 2012-07-18 |
Family
ID=40563909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007270259A Expired - Fee Related JP4976977B2 (ja) | 2007-10-17 | 2007-10-17 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7732338B2 (enExample) |
| JP (1) | JP4976977B2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100881513B1 (ko) * | 2007-05-18 | 2009-02-05 | 주식회사 동부하이텍 | 반도체 미세패턴 형성 방법 |
| US8420542B2 (en) * | 2011-05-27 | 2013-04-16 | International Business Machines Corporation | Method of patterned image reversal |
| WO2013089727A1 (en) * | 2011-12-15 | 2013-06-20 | Intel Corporation | Methods for single exposure - self-aligned double, triple, and quadruple patterning |
| CN103311092B (zh) * | 2012-03-12 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | 沟槽的刻蚀方法 |
| US9153440B2 (en) * | 2012-03-23 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
| CN103779263B (zh) * | 2012-10-18 | 2017-03-08 | 中芯国际集成电路制造(上海)有限公司 | 一种基于自对准双图案的半导体器件的制造方法 |
| CN103794476B (zh) * | 2012-10-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | 自对准三重图形的形成方法 |
| US9070559B2 (en) | 2013-07-25 | 2015-06-30 | Kabushiki Kaisha Toshiba | Pattern forming method and method of manufacturing semiconductor device |
| US9613806B2 (en) * | 2013-09-04 | 2017-04-04 | Sandisk Technologies Llc | Triple patterning NAND flash memory |
| CN103928313B (zh) * | 2014-04-22 | 2017-12-15 | 上海华力微电子有限公司 | 一种小尺寸图形的制作方法 |
| CN103928314B (zh) * | 2014-04-22 | 2017-06-06 | 上海华力微电子有限公司 | 一种底部无负载的自对准双层图形的制作方法 |
| CN109643639B (zh) * | 2016-09-13 | 2023-08-11 | 应用材料公司 | 用于间隔件和硬掩模应用的硼烷介导的从硅烷和烷基硅烷物质脱氢的工艺 |
| CN110690117B (zh) * | 2018-07-05 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| CN111819691B (zh) | 2020-05-25 | 2021-04-16 | 长江存储科技有限责任公司 | 存储器件及其形成方法 |
| CN111758159B (zh) * | 2020-05-25 | 2021-04-27 | 长江存储科技有限责任公司 | 存储器件及其形成方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748237A (en) * | 1980-09-05 | 1982-03-19 | Nec Corp | Manufacture of 2n doubling pattern |
| US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
| WO2001095690A1 (en) * | 2000-06-06 | 2001-12-13 | Ekc Technology, Inc. | Method of making electronic materials |
| US6429123B1 (en) * | 2000-10-04 | 2002-08-06 | Vanguard International Semiconductor Corporation | Method of manufacturing buried metal lines having ultra fine features |
| JP2002280388A (ja) * | 2001-03-15 | 2002-09-27 | Toshiba Corp | 半導体装置の製造方法 |
| JP2002359308A (ja) * | 2001-06-01 | 2002-12-13 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
| US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
| JP2006032648A (ja) * | 2004-07-16 | 2006-02-02 | Toshiba Corp | パターン形成方法を含む半導体装置の製造方法 |
| US7910288B2 (en) * | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
| JP4619839B2 (ja) * | 2005-03-16 | 2011-01-26 | 株式会社東芝 | パターン形成方法 |
| US7291560B2 (en) * | 2005-08-01 | 2007-11-06 | Infineon Technologies Ag | Method of production pitch fractionizations in semiconductor technology |
| US7575992B2 (en) * | 2005-09-14 | 2009-08-18 | Hynix Semiconductor Inc. | Method of forming micro patterns in semiconductor devices |
| KR100744683B1 (ko) * | 2006-02-27 | 2007-08-01 | 주식회사 하이닉스반도체 | 반도체 소자 제조 방법 |
| KR100790999B1 (ko) * | 2006-10-17 | 2008-01-03 | 삼성전자주식회사 | 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법 |
| KR100817088B1 (ko) * | 2007-02-16 | 2008-03-26 | 삼성전자주식회사 | 다마신 공정을 이용한 반도체 소자의 미세 금속 배선 패턴형성 방법 |
| KR100822592B1 (ko) * | 2007-03-23 | 2008-04-16 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
-
2007
- 2007-10-17 JP JP2007270259A patent/JP4976977B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-15 US US12/251,791 patent/US7732338B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2009099792A5 (enExample) | ||
| CN104733291B (zh) | 用于集成电路图案化的方法 | |
| US8298954B1 (en) | Sidewall image transfer process employing a cap material layer for a metal nitride layer | |
| TWI302635B (en) | Partially formed integrated circuit and method of integrated circuit fabrication and forming an integrated circuit | |
| TWI409852B (zh) | 利用自對準雙重圖案製作半導體元件微細結構的方法 | |
| JP2011502353A5 (enExample) | ||
| JP2006505949A5 (enExample) | ||
| JP2010503206A5 (enExample) | ||
| JP2007311584A5 (enExample) | ||
| CN104900495B (zh) | 自对准双重图形化方法及鳍式场效应晶体管的制作方法 | |
| US20140024219A1 (en) | Image transfer process employing a hard mask layer | |
| JP2007504679A5 (enExample) | ||
| JP2008258565A (ja) | 半導体素子の微細パターン形成方法 | |
| JP2008177606A5 (enExample) | ||
| CN101546693A (zh) | 半导体装置精细构图方法 | |
| CN104347517B (zh) | 半导体结构的形成方法 | |
| TWI567785B (zh) | 半導體裝置圖案化結構之製作方法 | |
| US8828876B2 (en) | Dual mandrel sidewall image transfer processes | |
| CN112864094A (zh) | 半导体结构及其形成方法 | |
| JP2007134598A5 (enExample) | ||
| KR100842763B1 (ko) | 반도체 소자의 미세 패턴 형성 방법 | |
| CN103311173A (zh) | 一种双深度浅沟道隔离槽的制备方法 | |
| CN103681899B (zh) | 提高感光密度的光敏器件及其制造方法 | |
| CN112018034A (zh) | 半导体结构及其形成方法 | |
| CN114388352A (zh) | 半导体结构及其形成方法 |