JP2009004756A - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP2009004756A
JP2009004756A JP2008127915A JP2008127915A JP2009004756A JP 2009004756 A JP2009004756 A JP 2009004756A JP 2008127915 A JP2008127915 A JP 2008127915A JP 2008127915 A JP2008127915 A JP 2008127915A JP 2009004756 A JP2009004756 A JP 2009004756A
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JP
Japan
Prior art keywords
crystal semiconductor
semiconductor layer
single crystal
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008127915A
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English (en)
Japanese (ja)
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JP2009004756A5 (zh
Inventor
Hidekazu Miyairi
秀和 宮入
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008127915A priority Critical patent/JP2009004756A/ja
Publication of JP2009004756A publication Critical patent/JP2009004756A/ja
Publication of JP2009004756A5 publication Critical patent/JP2009004756A5/ja
Withdrawn legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
JP2008127915A 2007-05-18 2008-05-15 半導体装置の作製方法 Withdrawn JP2009004756A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008127915A JP2009004756A (ja) 2007-05-18 2008-05-15 半導体装置の作製方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007132540 2007-05-18
JP2008127915A JP2009004756A (ja) 2007-05-18 2008-05-15 半導体装置の作製方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014094751A Division JP2014170959A (ja) 2007-05-18 2014-05-01 半導体装置の作製方法

Publications (2)

Publication Number Publication Date
JP2009004756A true JP2009004756A (ja) 2009-01-08
JP2009004756A5 JP2009004756A5 (zh) 2011-05-06

Family

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Family Applications (2)

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JP2008127915A Withdrawn JP2009004756A (ja) 2007-05-18 2008-05-15 半導体装置の作製方法
JP2014094751A Withdrawn JP2014170959A (ja) 2007-05-18 2014-05-01 半導体装置の作製方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2014094751A Withdrawn JP2014170959A (ja) 2007-05-18 2014-05-01 半導体装置の作製方法

Country Status (4)

Country Link
US (1) US7960262B2 (zh)
JP (2) JP2009004756A (zh)
CN (1) CN101308772B (zh)
TW (1) TWI476927B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020516085A (ja) * 2017-03-31 2020-05-28 アールエヌアール ラボラトリー インコーポレイテッド レーザを用いた間接加熱方法
US10836633B2 (en) 2015-12-28 2020-11-17 Hitachi Zosen Corporation Carbon nanotube composite material and method for producing carbon nanotube composite material

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* Cited by examiner, † Cited by third party
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US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5654206B2 (ja) 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Soi基板の作製方法及び該soi基板を用いた半導体装置
JP2009260315A (ja) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Soi基板の作製方法及び半導体装置の作製方法
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Soi基板の作製方法
SG161151A1 (en) * 2008-10-22 2010-05-27 Semiconductor Energy Lab Soi substrate and method for manufacturing the same
SG162675A1 (en) * 2008-12-15 2010-07-29 Semiconductor Energy Lab Manufacturing method of soi substrate and manufacturing method of semiconductor device
WO2013054823A1 (en) * 2011-10-14 2013-04-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP6743752B2 (ja) 2017-04-20 2020-08-19 三菱電機株式会社 半導体装置の製造方法
CN107833924B (zh) * 2017-10-26 2020-06-19 京东方科技集团股份有限公司 顶栅型薄膜晶体管及其制备方法、阵列基板、显示面板

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JP2000216265A (ja) * 1999-01-22 2000-08-04 Mega Chips Corp 半導体装置及びその製造方法
JP2001318652A (ja) * 2000-05-08 2001-11-16 Matsushita Electric Ind Co Ltd アクティブマトリクス液晶表示素子
JP2003282885A (ja) * 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP2006121060A (ja) * 2004-09-24 2006-05-11 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法、並びに電子機器
WO2006117900A1 (ja) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha 半導体装置の製造方法及び半導体装置
JP2007036216A (ja) * 2005-06-24 2007-02-08 Semiconductor Energy Lab Co Ltd 半導体装置及び無線通信システム
JP2007079431A (ja) * 2005-09-16 2007-03-29 Toshiba Matsushita Display Technology Co Ltd 表示素子用アレイ基板及びその作製方法、これを用いた表示素子

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JP3067949B2 (ja) 1994-06-15 2000-07-24 シャープ株式会社 電子装置および液晶表示装置
US6534380B1 (en) 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH1197379A (ja) 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
JP4101409B2 (ja) * 1999-08-19 2008-06-18 シャープ株式会社 半導体装置の製造方法
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CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
KR101457656B1 (ko) 2007-05-17 2014-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치의 제조방법, 표시장치의 제조방법, 반도체장치,표시장치 및 전자기기
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Publication number Priority date Publication date Assignee Title
JP2000216265A (ja) * 1999-01-22 2000-08-04 Mega Chips Corp 半導体装置及びその製造方法
JP2001318652A (ja) * 2000-05-08 2001-11-16 Matsushita Electric Ind Co Ltd アクティブマトリクス液晶表示素子
JP2003282885A (ja) * 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP2006121060A (ja) * 2004-09-24 2006-05-11 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法、並びに電子機器
WO2006117900A1 (ja) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha 半導体装置の製造方法及び半導体装置
JP2007036216A (ja) * 2005-06-24 2007-02-08 Semiconductor Energy Lab Co Ltd 半導体装置及び無線通信システム
JP2007079431A (ja) * 2005-09-16 2007-03-29 Toshiba Matsushita Display Technology Co Ltd 表示素子用アレイ基板及びその作製方法、これを用いた表示素子

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10836633B2 (en) 2015-12-28 2020-11-17 Hitachi Zosen Corporation Carbon nanotube composite material and method for producing carbon nanotube composite material
US11414321B2 (en) 2015-12-28 2022-08-16 Hitachi Zosen Corporation Carbon nanotube composite material and method for producing carbon nanotube composite material
JP2020516085A (ja) * 2017-03-31 2020-05-28 アールエヌアール ラボラトリー インコーポレイテッド レーザを用いた間接加熱方法

Also Published As

Publication number Publication date
TWI476927B (zh) 2015-03-11
US7960262B2 (en) 2011-06-14
CN101308772B (zh) 2013-01-02
JP2014170959A (ja) 2014-09-18
TW200903811A (en) 2009-01-16
CN101308772A (zh) 2008-11-19
US20080286911A1 (en) 2008-11-20

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