JP2008546168A - 論理セルのセル隣接により形成された信号バスを有する集積回路 - Google Patents
論理セルのセル隣接により形成された信号バスを有する集積回路 Download PDFInfo
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- JP2008546168A JP2008546168A JP2008511396A JP2008511396A JP2008546168A JP 2008546168 A JP2008546168 A JP 2008546168A JP 2008511396 A JP2008511396 A JP 2008511396A JP 2008511396 A JP2008511396 A JP 2008511396A JP 2008546168 A JP2008546168 A JP 2008546168A
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- 239000004065 semiconductor Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 230000008901 benefit Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000006978 adaptation Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003915 cell function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Evolutionary Computation (AREA)
- Computing Systems (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (23)
- 少なくとも2つの論理セル;及び
前記少なくとも2つの論理セルのセル隣接によって形成され、且つ信号を受信し該信号を前記少なくとも2つの論理セルの各々に分配するように構成された信号バス;
を有する集積回路。 - 前記信号バスは前記少なくとも2つの論理セルを横切って延在している、請求項1に記載の集積回路。
- 前記信号バスは第1の半導体層から形成されている、請求項1に記載の集積回路。
- 前記第1の半導体層は多結晶シリコン層から成る、請求項3に記載の集積回路。
- 前記信号バスは、前記少なくとも2つの論理セルの各々にスリープ信号を分配するように構成されたスリープバスを有する、請求項1に記載の集積回路。
- 前記スリープバスに結合され、且つ前記スリープ信号を受信するように構成されたスリープピン、を更に有する請求項5に記載の集積回路。
- 前記少なくとも2つの論理セルに結合され、且つ前記スリープバスから前記スリープ信号を受信し、該スリープ信号に基づいて前記少なくとも2つの論理セルにおける電力消費を制御するように構成されたスリープ回路、を更に有する請求項5に記載の集積回路。
- 前記スリープ回路は1つ以上のスリープトランジスタを有する、請求項7に記載の集積回路。
- 前記1つ以上のスリープトランジスタのドレインは第2の半導体層から形成されている、請求項8に記載の集積回路。
- 前記1つ以上のスリープトランジスタはNMOSトランジスタから成る、請求項8に記載の集積回路。
- 前記1つ以上のスリープトランジスタはPMOSトランジスタから成る、請求項8に記載の集積回路。
- 少なくとも2つの論理セルのセル隣接によって形成された信号バスを用いて信号を受信する段階;及び
前記少なくとも2つの論理セルの各々に前記信号を分配する段階;
を有する方法。 - 前記信号バスは前記少なくとも2つの論理セルを横切って延在している、請求項12に記載の方法。
- 前記信号を分配する段階は、第1の半導体層から形成された前記信号バスを用いることを有する、請求項12に記載の方法。
- 前記第1の半導体層は多結晶シリコン層から成る、請求項14に記載の方法。
- 前記信号を分配する段階は、前記少なくとも2つの論理セルの各々にスリープ信号を分配するように構成されたスリープバスを用いることを有する、請求項12に記載の方法。
- 前記スリープバスに結合されたスリープピンから前記スリープ信号を受信する段階、を更に有する請求項16に記載の方法。
- 前記スリープ信号を分配する段階は、前記少なくとも2つの論理セルにおける電力消費を制御するように構成されたスリープ回路を用いることを有する、請求項16に記載の方法。
- 前記スリープ回路は1つ以上のスリープトランジスタを有する、請求項18に記載の方法。
- 前記1つ以上のスリープトランジスタのドレインは第2の半導体層から形成されている、請求項19に記載の方法。
- 前記1つ以上のスリープトランジスタはNMOSトランジスタから成る、請求項19に記載の方法。
- 前記1つ以上のスリープトランジスタはPMOSトランジスタから成る、請求項19に記載の方法。
- 少なくとも2つの論理セル;及び
前記少なくとも2つの論理セルのセル隣接によって形成され、且つ信号を受信し該信号を前記少なくとも2つの論理セルの各々に分配するように構成された信号バス;
を有する標準セル・ライブラリー。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US68088805P | 2005-05-13 | 2005-05-13 | |
US60/680,888 | 2005-05-13 | ||
PCT/US2006/018409 WO2006124576A2 (en) | 2005-05-13 | 2006-05-12 | Integrated circuit with signal bus formed by cell abutment of logic cells |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008546168A true JP2008546168A (ja) | 2008-12-18 |
JP2008546168A5 JP2008546168A5 (ja) | 2011-12-01 |
JP5096321B2 JP5096321B2 (ja) | 2012-12-12 |
Family
ID=37431904
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008511396A Expired - Fee Related JP5096321B2 (ja) | 2005-05-13 | 2006-05-12 | 論理セルのセル隣接により形成された信号バスを有する集積回路 |
Country Status (8)
Country | Link |
---|---|
US (2) | US7508256B2 (ja) |
EP (1) | EP1882307B1 (ja) |
JP (1) | JP5096321B2 (ja) |
KR (1) | KR101281440B1 (ja) |
CN (1) | CN101558492B (ja) |
CA (1) | CA2608323A1 (ja) |
TW (1) | TWI414149B (ja) |
WO (1) | WO2006124576A2 (ja) |
Cited By (1)
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WO2010122754A1 (ja) * | 2009-04-22 | 2010-10-28 | パナソニック株式会社 | 半導体集積回路 |
Families Citing this family (18)
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US8074086B1 (en) * | 2006-12-11 | 2011-12-06 | Cypress Semiconductor Corporation | Circuit and method for dynamic in-rush current control in a power management circuit |
US8421499B2 (en) * | 2010-02-15 | 2013-04-16 | Apple Inc. | Power switch ramp rate control using programmable connection to switches |
US8362805B2 (en) * | 2010-02-15 | 2013-01-29 | Apple Inc. | Power switch ramp rate control using daisy-chained flops |
TWI405093B (zh) * | 2010-08-30 | 2013-08-11 | Global Unichip Corp | 半導體元件庫之鄰接圖樣樣板結構 |
EP2429079B1 (en) * | 2010-09-10 | 2015-01-07 | Apple Inc. | Configurable power switch cells and methodology |
US8504967B2 (en) * | 2010-09-10 | 2013-08-06 | Apple Inc. | Configurable power switch cells and methodology |
US8451026B2 (en) * | 2011-05-13 | 2013-05-28 | Arm Limited | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells |
US8813016B1 (en) | 2013-01-28 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company Limited | Multiple via connections using connectivity rings |
US9786645B2 (en) | 2013-11-06 | 2017-10-10 | Mediatek Inc. | Integrated circuit |
US9348963B1 (en) * | 2014-09-30 | 2016-05-24 | Cadence Design System, Inc. | Automatic abutment for devices with horizontal pins |
US9842182B2 (en) | 2014-10-01 | 2017-12-12 | Samsung Electronics Co., Ltd. | Method and system for designing semiconductor device |
WO2016075859A1 (ja) * | 2014-11-12 | 2016-05-19 | 株式会社ソシオネクスト | 半導体集積回路のレイアウト構造 |
US9564898B2 (en) | 2015-02-13 | 2017-02-07 | Apple Inc. | Power switch ramp rate control using selectable daisy-chained connection of enable to power switches or daisy-chained flops providing enables |
US9640480B2 (en) * | 2015-05-27 | 2017-05-02 | Qualcomm Incorporated | Cross-couple in multi-height sequential cells for uni-directional M1 |
US10068918B2 (en) | 2015-09-21 | 2018-09-04 | Globalfoundries Inc. | Contacting SOI subsrates |
CN108292658A (zh) * | 2015-09-25 | 2018-07-17 | 英特尔公司 | 局部单元级别功率门控开关 |
US10784198B2 (en) * | 2017-03-20 | 2020-09-22 | Samsung Electronics Co., Ltd. | Power rail for standard cell block |
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2006
- 2006-05-12 JP JP2008511396A patent/JP5096321B2/ja not_active Expired - Fee Related
- 2006-05-12 WO PCT/US2006/018409 patent/WO2006124576A2/en active Application Filing
- 2006-05-12 CA CA002608323A patent/CA2608323A1/en not_active Abandoned
- 2006-05-12 CN CN2006800209275A patent/CN101558492B/zh not_active Expired - Fee Related
- 2006-05-12 EP EP06770268.8A patent/EP1882307B1/en not_active Not-in-force
- 2006-05-12 US US11/433,158 patent/US7508256B2/en active Active
- 2006-05-12 KR KR1020077029220A patent/KR101281440B1/ko not_active IP Right Cessation
- 2006-05-15 TW TW095117110A patent/TWI414149B/zh not_active IP Right Cessation
-
2009
- 2009-02-10 US US12/368,512 patent/US8026738B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
US7508256B2 (en) | 2009-03-24 |
JP5096321B2 (ja) | 2012-12-12 |
WO2006124576A2 (en) | 2006-11-23 |
KR20080070522A (ko) | 2008-07-30 |
US20090140800A1 (en) | 2009-06-04 |
US20060261855A1 (en) | 2006-11-23 |
CN101558492B (zh) | 2011-10-19 |
TW200742253A (en) | 2007-11-01 |
WO2006124576A3 (en) | 2009-04-16 |
KR101281440B1 (ko) | 2013-07-02 |
EP1882307A4 (en) | 2009-12-30 |
EP1882307A2 (en) | 2008-01-30 |
US8026738B2 (en) | 2011-09-27 |
CA2608323A1 (en) | 2006-11-23 |
TWI414149B (zh) | 2013-11-01 |
CN101558492A (zh) | 2009-10-14 |
EP1882307B1 (en) | 2013-07-31 |
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