JP2008541657A - 高速回路のデータエッジ−クロックエッジ位相検出器 - Google Patents
高速回路のデータエッジ−クロックエッジ位相検出器 Download PDFInfo
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- JP2008541657A JP2008541657A JP2008512267A JP2008512267A JP2008541657A JP 2008541657 A JP2008541657 A JP 2008541657A JP 2008512267 A JP2008512267 A JP 2008512267A JP 2008512267 A JP2008512267 A JP 2008512267A JP 2008541657 A JP2008541657 A JP 2008541657A
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- 230000000630 rising effect Effects 0.000 claims description 4
- 238000005191 phase separation Methods 0.000 claims description 3
- 230000000977 initiatory effect Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 description 11
- 238000013461 design Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 230000003068 static effect Effects 0.000 description 4
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- 108010076504 Protein Sorting Signals Proteins 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
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- 238000012545 processing Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
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- 238000004088 simulation Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
【選択図】図1
Description
本発明は、米空軍研究所から与えられた契約F29601−98−9−0193の下で部分的に米国政府の援助を受けてなされたものである。したがって、米国政府は本発明に一定の権利を所有することができる。
Claims (7)
- クロック信号遷移とデータ信号遷移との間に相対位相を確立する方法であって、
同じ周波数を有する複数のクロック信号を作成するステップであって、前記各クロック信号が異なる相対位相を有するステップと、
前記クロック信号に従って一連のタイミングビンを確立するステップと、
前記一連のタイミングビンを有効タイミングビンおよび無効タイミングビンに分けるステップと、
リンクインタフェースからデータ遷移を有するデータ信号を受け取るステップであって、前記データ信号がデータ位相を有するステップと、
前記データ遷移が有効タイミングビン中に発生したか、それとも無効タイミングビン中に発生したかを判断するステップと
を含む方法。 - 各タイミングビンは、前記複数のクロック信号の一意のシーケンスに対応する、請求項1に記載の方法。
- 各タイミングビンは、前記クロック信号のうちの1つの立ち上がりエッジで始まり、続く相対位相を有する前記クロック信号の立ち上がりエッジで終わる、請求項2に記載の方法。
- 前記複数のクロック信号はそれぞれ位相分離2π/Nラジアンを有し、Nはクロック信号数である、請求項1に記載の方法。
- 前記ヒットタイミングビンが有効タイミングビンであるか、それとも無効タイミングビンであるかを判断するステップをさらに含む、請求項1に記載の方法。
- 前記ヒットタイミングビンが無効タイミングビンである場合、前記リンクの再トレーニングプロセスを開始するステップをさらに含む、請求項5に記載の方法。
- 前記再トレーニングプロセスは、
一連のテスト信号を前記リンクインタフェースにおいて生成するステップであって、各テスト信号は遷移を有し、異なる位相を有するステップと、
各テスト信号を宛先で受け取るステップと、
各テスト信号が遷移を有効タイミングビン中に有するか、それとも無効タイミングビン中に有するのかを判断するステップと、
前記テスト信号が有効タイミングビン中に遷移する場合のみ、各テスト信号を有効テスト信号に分類するステップと、
前記データ位相を有効テスト信号の位相にセットするように前記リンクインタフェースに命令するステップと
を含む、請求項6に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/134,099 US7555089B2 (en) | 2005-05-20 | 2005-05-20 | Data edge-to-clock edge phase detector for high speed circuits |
US11/134,099 | 2005-05-20 | ||
PCT/US2006/005196 WO2006127068A1 (en) | 2005-05-20 | 2006-02-15 | Data edge-to-clock edge phase detector for high speed circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008541657A true JP2008541657A (ja) | 2008-11-20 |
JP5362351B2 JP5362351B2 (ja) | 2013-12-11 |
Family
ID=36753983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008512267A Expired - Fee Related JP5362351B2 (ja) | 2005-05-20 | 2006-02-15 | 高速回路のデータエッジ−クロックエッジ位相検出器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7555089B2 (ja) |
EP (1) | EP1884057B1 (ja) |
JP (1) | JP5362351B2 (ja) |
DE (1) | DE602006011879D1 (ja) |
WO (1) | WO2006127068A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8138799B2 (en) | 2009-12-28 | 2012-03-20 | Nec Corporation | Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7861105B2 (en) * | 2007-06-25 | 2010-12-28 | Analogix Semiconductor, Inc. | Clock data recovery (CDR) system using interpolator and timing loop module |
US8587337B1 (en) * | 2009-01-31 | 2013-11-19 | Xilinx, Inc. | Method and apparatus for capturing and synchronizing data |
US8207763B1 (en) * | 2010-06-29 | 2012-06-26 | The United States Of America As Represented By The Secretary Of The Navy | Non-linear channelizer device with wideband, high-frequency operation and channel reconfigurability |
TWI469522B (zh) * | 2011-01-06 | 2015-01-11 | Raydium Semiconductor Corp | 訊號電路 |
US10218360B2 (en) * | 2016-08-02 | 2019-02-26 | Altera Corporation | Dynamic clock-data phase alignment in a source synchronous interface circuit |
CN110710152B (zh) * | 2017-06-29 | 2022-02-18 | 新唐科技日本株式会社 | 时钟恢复系统 |
KR102637731B1 (ko) | 2017-12-26 | 2024-02-19 | 삼성전자주식회사 | 데이터 라인 구동 회로, 이를 포함하는 디스플레이 구동 회로 및 디스플레이 구동 방법 |
US11956340B1 (en) * | 2022-09-29 | 2024-04-09 | Texas Instruments Incorporated | Methods and apparatus to reduce retimer latency and jitter |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0416032A (ja) * | 1990-05-10 | 1992-01-21 | Nec Corp | ビット位相同期回路 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0306002B1 (de) | 1987-09-01 | 1992-04-15 | Siemens Aktiengesellschaft | Verfahren zur adaptiven Phasenanpassung in einer taktsynchron betriebenen Breitband-Digitalsignal-Koppelanordnung |
US4876699A (en) | 1988-05-06 | 1989-10-24 | Rockwell International Corporation | High speed sampled data digital phase detector apparatus |
EP0671829B1 (en) | 1994-03-11 | 2006-06-28 | Fujitsu Limited | Clock regeneration circuit |
US6100733A (en) | 1998-06-09 | 2000-08-08 | Siemens Aktiengesellschaft | Clock latency compensation circuit for DDR timing |
FR2781943B1 (fr) | 1998-07-30 | 2000-09-15 | Thomson Multimedia Sa | Procede de recuperation d'horloge lors de l'echantillonnage de signaux de type numerique |
US6784707B2 (en) | 2002-07-10 | 2004-08-31 | The Board Of Trustees Of The University Of Illinois | Delay locked loop clock generator |
-
2005
- 2005-05-20 US US11/134,099 patent/US7555089B2/en active Active
-
2006
- 2006-02-15 DE DE602006011879T patent/DE602006011879D1/de active Active
- 2006-02-15 WO PCT/US2006/005196 patent/WO2006127068A1/en active Application Filing
- 2006-02-15 EP EP06735046A patent/EP1884057B1/en not_active Expired - Fee Related
- 2006-02-15 JP JP2008512267A patent/JP5362351B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0416032A (ja) * | 1990-05-10 | 1992-01-21 | Nec Corp | ビット位相同期回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8138799B2 (en) | 2009-12-28 | 2012-03-20 | Nec Corporation | Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
DE602006011879D1 (de) | 2010-03-11 |
JP5362351B2 (ja) | 2013-12-11 |
EP1884057B1 (en) | 2010-01-20 |
EP1884057A1 (en) | 2008-02-06 |
US20060262891A1 (en) | 2006-11-23 |
WO2006127068A1 (en) | 2006-11-30 |
US7555089B2 (en) | 2009-06-30 |
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