DE602006011879D1 - Daten-flanken-zu-takt-flankenphasendetektor für schnelle schaltungen - Google Patents

Daten-flanken-zu-takt-flankenphasendetektor für schnelle schaltungen

Info

Publication number
DE602006011879D1
DE602006011879D1 DE602006011879T DE602006011879T DE602006011879D1 DE 602006011879 D1 DE602006011879 D1 DE 602006011879D1 DE 602006011879 T DE602006011879 T DE 602006011879T DE 602006011879 T DE602006011879 T DE 602006011879T DE 602006011879 D1 DE602006011879 D1 DE 602006011879D1
Authority
DE
Germany
Prior art keywords
flank
phase detector
take
data
fast circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006011879T
Other languages
English (en)
Inventor
Raymond G Faulkner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Publication of DE602006011879D1 publication Critical patent/DE602006011879D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE602006011879T 2005-05-20 2006-02-15 Daten-flanken-zu-takt-flankenphasendetektor für schnelle schaltungen Active DE602006011879D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/134,099 US7555089B2 (en) 2005-05-20 2005-05-20 Data edge-to-clock edge phase detector for high speed circuits
PCT/US2006/005196 WO2006127068A1 (en) 2005-05-20 2006-02-15 Data edge-to-clock edge phase detector for high speed circuits

Publications (1)

Publication Number Publication Date
DE602006011879D1 true DE602006011879D1 (de) 2010-03-11

Family

ID=36753983

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006011879T Active DE602006011879D1 (de) 2005-05-20 2006-02-15 Daten-flanken-zu-takt-flankenphasendetektor für schnelle schaltungen

Country Status (5)

Country Link
US (1) US7555089B2 (de)
EP (1) EP1884057B1 (de)
JP (1) JP5362351B2 (de)
DE (1) DE602006011879D1 (de)
WO (1) WO2006127068A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7861105B2 (en) * 2007-06-25 2010-12-28 Analogix Semiconductor, Inc. Clock data recovery (CDR) system using interpolator and timing loop module
US8742791B1 (en) * 2009-01-31 2014-06-03 Xilinx, Inc. Method and apparatus for preamble detection for a control signal
JP5347955B2 (ja) * 2009-12-28 2013-11-20 日本電気株式会社 多相クロック間の相間スキュー検出回路、相間スキュー調整回路、および半導体集積回路
US8207763B1 (en) * 2010-06-29 2012-06-26 The United States Of America As Represented By The Secretary Of The Navy Non-linear channelizer device with wideband, high-frequency operation and channel reconfigurability
TWI469522B (zh) * 2011-01-06 2015-01-11 Raydium Semiconductor Corp 訊號電路
US10218360B2 (en) * 2016-08-02 2019-02-26 Altera Corporation Dynamic clock-data phase alignment in a source synchronous interface circuit
JP6945198B2 (ja) * 2017-06-29 2021-10-06 ヌヴォトンテクノロジージャパン株式会社 クロックリカバリシステム
KR102637731B1 (ko) 2017-12-26 2024-02-19 삼성전자주식회사 데이터 라인 구동 회로, 이를 포함하는 디스플레이 구동 회로 및 디스플레이 구동 방법
US11956340B1 (en) * 2022-09-29 2024-04-09 Texas Instruments Incorporated Methods and apparatus to reduce retimer latency and jitter

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0306002B1 (de) 1987-09-01 1992-04-15 Siemens Aktiengesellschaft Verfahren zur adaptiven Phasenanpassung in einer taktsynchron betriebenen Breitband-Digitalsignal-Koppelanordnung
US4876699A (en) 1988-05-06 1989-10-24 Rockwell International Corporation High speed sampled data digital phase detector apparatus
JPH0416032A (ja) * 1990-05-10 1992-01-21 Nec Corp ビット位相同期回路
DE69535087T2 (de) 1994-03-11 2006-12-21 Fujitsu Ltd., Kawasaki Schaltungsanordnung zur Taktrückgewinnung
US6100733A (en) 1998-06-09 2000-08-08 Siemens Aktiengesellschaft Clock latency compensation circuit for DDR timing
FR2781943B1 (fr) 1998-07-30 2000-09-15 Thomson Multimedia Sa Procede de recuperation d'horloge lors de l'echantillonnage de signaux de type numerique
US6784707B2 (en) 2002-07-10 2004-08-31 The Board Of Trustees Of The University Of Illinois Delay locked loop clock generator

Also Published As

Publication number Publication date
JP2008541657A (ja) 2008-11-20
US20060262891A1 (en) 2006-11-23
EP1884057A1 (de) 2008-02-06
JP5362351B2 (ja) 2013-12-11
WO2006127068A1 (en) 2006-11-30
US7555089B2 (en) 2009-06-30
EP1884057B1 (de) 2010-01-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition