JP2008530816A - 2枚の半導体基板のアルミニウム電極の接合方法 - Google Patents
2枚の半導体基板のアルミニウム電極の接合方法 Download PDFInfo
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Abstract
【課題】2枚の半導体基板上に形成された回路などに影響しない低い温度で、半導体製造設備の汚染なしに、2枚の半導体基板上に形成されたアルミニウム(Al)電極を接合させる方法を提供する。
【解決手段】本発明による2枚の半導体基板のアルミニウム(Al)電極の接合方法は、(a)2枚の半導体基板の各々にアルミニウム(Al)電極を形成し、前記アルミニウム(Al)電極にアルミニウム(Al)と銅(Cu)とから構成された金属合金を蒸着する工程;(b)前記2枚の半導体基板のアルミニウム(Al)電極を対向するように配置する工程と;(c)前記アルミニウム(Al)電極に蒸着された金属合金の融点より低い温度に加熱し、前記2枚の半導体基板に所定の圧力を加える工程と;を含むことを特徴とする。本発明によれば、2枚の半導体基板上に形成された回路などに影響しないように、Al0.83Cu0.17合金の融点より低い温度で接合を進むことができ、圧力を受ける部分だけを選択的に接合することが可能である。
【選択図】図2
【解決手段】本発明による2枚の半導体基板のアルミニウム(Al)電極の接合方法は、(a)2枚の半導体基板の各々にアルミニウム(Al)電極を形成し、前記アルミニウム(Al)電極にアルミニウム(Al)と銅(Cu)とから構成された金属合金を蒸着する工程;(b)前記2枚の半導体基板のアルミニウム(Al)電極を対向するように配置する工程と;(c)前記アルミニウム(Al)電極に蒸着された金属合金の融点より低い温度に加熱し、前記2枚の半導体基板に所定の圧力を加える工程と;を含むことを特徴とする。本発明によれば、2枚の半導体基板上に形成された回路などに影響しないように、Al0.83Cu0.17合金の融点より低い温度で接合を進むことができ、圧力を受ける部分だけを選択的に接合することが可能である。
【選択図】図2
Description
本発明は、半導体製造工程に関し、特に、半導体の製造工程において、2枚の基板を重ね合う場合における、金属配線の接合方法に関する。
半導体製造工程において、電極を接合する場合、一般的に、融点が低い鉛(Pb)、スズ(Sn)、ビスマス(Bi)などの合金を使用するが、このような物質は、人体に有害であり、一般的に蒸気圧が低く、半導体製造設備を汚染させるため、半導体製造工程において使用できないという短所がある。
殆どの半導体製造工程において、金属電極としてアルミニウム(Al)を使用するが、このようなアルミニウム(Al)を使用する工程において、2枚の基板を重ねってアルミニウム(Al)電極を接合する場合、アルミニウム(Al)の電極を融点近くまで上げて接合することが可能であり、この場合、接合しようとする部分以外の部分の電極が一緒に溶けるので、既に存在する基板上の配線や回路に悪影響を与える。
本発明が達成しようとする技術的課題は、2枚の半導体基板上に形成された回路などに影響しない低い温度で、半導体製造設備の汚染なしに、2枚の半導体基板上に形成されたアルミニウム(Al)電極を接合させる方法を提供することにある。
前記技術的課題を解決するための本発明による2枚の半導体基板のアルミニウム(Al)電極の接合方法は、(a)2枚の半導体基板の各々にアルミニウム(Al)電極を形成し、前記アルミニウム(Al)電極にアルミニウム(Al)と銅(Cu)とから構成された金属合金を蒸着する工程;(b)前記2枚の半導体基板のアルミニウム(Al)電極を対向するように配置する工程;(c)前記アルミニウム(Al)電極に蒸着された合金の融点より低い温度で加熱し、前記2枚の半導体基板に所定の圧力を加える工程と;を含むことを特徴とする。
また、前記金属合金は、Al0.83Cu0.17であることを特徴とする。
本発明によれば、2枚の半導体基板上に形成された回路などに影響しないように、Al0.83Cu0.17合金の融点より低い温度で接合を進めることができ、圧力を受ける部分のみを選択的に接合することが可能である。
以下、図面を参照して、本発明を詳細に説明するようにする。
図1〜図3は、本発明に係る2枚の半導体基板上に形成されたアルミニウム(Al)電極の接合過程を示したものである。
図1は、2枚の半導体基板に形成されたAl電極を示したものである。
半導体基板(10、20)上に、接合しようとするAl電極(13、23)を形成し、その上に、Al0.83Cu0.17合金(15、25)を蒸着する。
図2は、2枚の半導体基板のAl電極が接合される過程を示したものである。
2枚の半導体基板(10、20)を接合しようとするAl電極(13、23)が重なるように配置した状態で、Al0.83Cu0.17合金(15、25)の融点より低い温度に加熱し、両半導体基板(10、20)に適当な圧力が加えられるようにする。
前記2枚の半導体基板(10、20)に適当な圧力を加えることにより、接合しようとする2つのAl電極(13、23)が圧力を受けるようになり、前記Al0.83Cu0.17合金(15、25)は、大気圧状態での融点より低い温度で溶けるようになる。
前記Al0.83Cu0.17合金(15、25)は、融点が約540℃とAl電極(13、23)の融点650℃よりずっと低く、溶融接合に有利である。また、前記Al0.83Cu0.17合金(15、25)は、AlとCuとが均一に混ざる特徴を有する。
図3は、2枚の半導体基板のAl電極が接合された状態を示したものである。
前記Al0.83Cu0.17合金(15、25)をAl電極(13、23)上に蒸着し、熱を加えると、合金が蒸着された面が、Al電極部分よりも速く溶けるようになるので、接合部以外の部分の熱的損傷を防止することができ、半導体製造工程において一般的に使用される代表的な金属であるAlとCuとの合金を使用するので、半導体製造工程上の汚染が生じない。
また、高温で塗布された合金において、Al電極へのCuの拡散は、Al電極の融点を下げる効果を与えるが、このような拡散によって形成された合金の融点は、元の合金の融点より高いので、接合に大きい影響を与えない。
以上から、本発明は、図面に図示された実施例を参考として説明されたが、これは、例示的なものに過ぎなく、本技術分野において通常の知識を有する者ならば、これらから様々な変形及び均等な他実施例が可能である点を理解されたい。従って、本発明の真の技術的な保護範囲は、添付の請求範囲の技術的な思想により定められるべきである。
10、20:2枚の半導体基板
13,23:Al電極
15,25: Al0.83Cu0.17合金
13,23:Al電極
15,25: Al0.83Cu0.17合金
Claims (3)
- 2枚の半導体基板のアルミニウム(Al)電極を接合する方法において、
(a) 前記2枚の半導体基板の各々にアルミニウム(Al)電極を形成し、前記アルミニウム(Al)電極にアルミニウム(Al)と銅(Cu)とから構成された金属合金を蒸着する工程と;
(b) 前記2枚の半導体基板のアルミニウム(Al)電極を対向するように配置する工程と;
(c) 前記アルミニウム(Al)電極に蒸着された金属合金の融点より低い温度に加熱し、前記2枚の半導体基板に所定の圧力を加える工程と;を含むことを特徴とする2枚の半導体基板のアルミニウム(Al)電極の接合方法。 - 前記金属合金は、
Al0.83Cu0.17であることを特徴とする請求項1に記載の2枚の半導体基板のアルミニウム(Al)電極の接合方法。 - 前記(c)工程での温度は、
540℃未満であることを特徴とする請求項1に記載の2枚の半導体基板のアルミニウム(Al)電極の接合方法。
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KR1020050017955A KR100591461B1 (ko) | 2005-03-04 | 2005-03-04 | 두 반도체 기판의 알루미늄 전극 접합방법 |
PCT/KR2006/000712 WO2006093386A1 (en) | 2005-03-04 | 2006-03-02 | Method of bonding aluminum electrodes of two semiconductor substrates |
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JP2008530816A true JP2008530816A (ja) | 2008-08-07 |
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US (1) | US7732300B2 (ja) |
EP (1) | EP1854135A4 (ja) |
JP (1) | JP2008530816A (ja) |
KR (1) | KR100591461B1 (ja) |
CN (1) | CN100508151C (ja) |
WO (1) | WO2006093386A1 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63107127A (ja) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | 半導体装置 |
JPH08506698A (ja) * | 1993-02-09 | 1996-07-16 | ナショナル・セミコンダクター・コーポレイション | 基板への半導体チップの接合方法 |
JPH11288977A (ja) * | 1998-03-31 | 1999-10-19 | Nippon Steel Corp | 複数チップ混載型半導体装置 |
JP2002111182A (ja) * | 2000-09-29 | 2002-04-12 | Katsuaki Suganuma | 導電性接着剤で接続した部品の易剥離法 |
JP2004288768A (ja) * | 2003-03-20 | 2004-10-14 | Mitsubishi Electric Corp | 多層配線基体の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4890784A (en) * | 1983-03-28 | 1990-01-02 | Rockwell International Corporation | Method for diffusion bonding aluminum |
US4854495A (en) * | 1986-06-20 | 1989-08-08 | Hitachi, Ltd. | Sealing structure, method of soldering and process for preparing sealing structure |
JP2835145B2 (ja) * | 1990-05-28 | 1998-12-14 | 株式会社東芝 | 電子装置 |
JPH06333983A (ja) * | 1993-05-19 | 1994-12-02 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
EP1056321B1 (en) * | 1999-05-28 | 2007-11-14 | Denki Kagaku Kogyo Kabushiki Kaisha | Ceramic substrate circuit and its manufacturing process |
KR100347762B1 (ko) * | 1999-12-15 | 2002-08-09 | 엘지전자주식회사 | 베어칩 반도체 집적회로 및 회로기판 패턴의 직접 접합 방법 |
JP3735526B2 (ja) * | 2000-10-04 | 2006-01-18 | 日本電気株式会社 | 半導体装置及びその製造方法 |
KR20030047085A (ko) * | 2001-12-07 | 2003-06-18 | 엘지전선 주식회사 | 니켈 금속을 연결수단으로 이용한 전자부품 및 접속방법 |
US7098072B2 (en) * | 2002-03-01 | 2006-08-29 | Agng, Llc | Fluxless assembly of chip size semiconductor packages |
US20060292823A1 (en) * | 2005-06-28 | 2006-12-28 | Shriram Ramanathan | Method and apparatus for bonding wafers |
-
2005
- 2005-03-04 KR KR1020050017955A patent/KR100591461B1/ko active IP Right Grant
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2006
- 2006-03-02 JP JP2007556090A patent/JP2008530816A/ja active Pending
- 2006-03-02 US US11/817,761 patent/US7732300B2/en active Active
- 2006-03-02 EP EP06716162A patent/EP1854135A4/en not_active Withdrawn
- 2006-03-02 CN CNB2006800066816A patent/CN100508151C/zh not_active Expired - Fee Related
- 2006-03-02 WO PCT/KR2006/000712 patent/WO2006093386A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63107127A (ja) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | 半導体装置 |
JPH08506698A (ja) * | 1993-02-09 | 1996-07-16 | ナショナル・セミコンダクター・コーポレイション | 基板への半導体チップの接合方法 |
JPH11288977A (ja) * | 1998-03-31 | 1999-10-19 | Nippon Steel Corp | 複数チップ混載型半導体装置 |
JP2002111182A (ja) * | 2000-09-29 | 2002-04-12 | Katsuaki Suganuma | 導電性接着剤で接続した部品の易剥離法 |
JP2004288768A (ja) * | 2003-03-20 | 2004-10-14 | Mitsubishi Electric Corp | 多層配線基体の製造方法 |
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EP1854135A1 (en) | 2007-11-14 |
EP1854135A4 (en) | 2012-05-02 |
US7732300B2 (en) | 2010-06-08 |
CN101133486A (zh) | 2008-02-27 |
US20080293184A1 (en) | 2008-11-27 |
KR100591461B1 (ko) | 2006-06-20 |
CN100508151C (zh) | 2009-07-01 |
WO2006093386A1 (en) | 2006-09-08 |
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