CN101133486A - 使两个半导体衬底的铝电极接合的方法 - Google Patents
使两个半导体衬底的铝电极接合的方法 Download PDFInfo
- Publication number
- CN101133486A CN101133486A CNA2006800066816A CN200680006681A CN101133486A CN 101133486 A CN101133486 A CN 101133486A CN A2006800066816 A CNA2006800066816 A CN A2006800066816A CN 200680006681 A CN200680006681 A CN 200680006681A CN 101133486 A CN101133486 A CN 101133486A
- Authority
- CN
- China
- Prior art keywords
- aluminium
- electrode
- semiconductor substrates
- semiconductor substrate
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 41
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000010949 copper Substances 0.000 claims abstract description 24
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 16
- 239000000956 alloy Substances 0.000 claims abstract description 16
- 229910001092 metal group alloy Inorganic materials 0.000 claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052802 copper Inorganic materials 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims abstract description 5
- 239000004411 aluminium Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910000743 fusible alloy Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81208—Compression bonding applying unidirectional static pressure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
本发明提供了一种在不影响两个半导体衬底上所形成电路的低温下使两个半导体衬底上形成的铝(Al)电极接合的方法。该方法包括:(a)分别在两个半导体衬底上形成铝(Al)电极,并在铝(Al)电极上沉积包含铝(Al)和铜(Cu)的金属合金;(b)使两个半导体衬底的铝(Al)电极面对面排列;(c)在低于已沉积的金属合金熔点的温度下对铝(Al)电极进行加热,并且在两个半导体衬底上施加一定的压力。因此,可在低于Al0.83Cu0.17合金熔点的温度完成接合,而不影响在两个半导体衬底上形成的电路,并且接合可在施加压力的区域内选择性地完成。
Description
技术领域
本发明涉及半导体制造工艺,特别涉及在制造半导体的工艺中接合两个叠置衬底的金属线的方法。
背景技术
通常,在半导体制造工艺中利用具有低熔点的合金,如铅(Pb)、锡(Sn)和铋(Bi),使多个电极接合。然而,此类合金对人体有害,并且由于较低的蒸气压而会污染半导体制造设备。
在大多数半导体制造工艺中,通常将铝(Al)用作金属电极。在接合铝(Al)电极以使在其中间具有铝(Al)电极的两个衬底被叠置的情况下,可将铝(Al)电极加热至邻近其熔点。由于对铝(Al)电极进行加热,所以不是接合区域的、铝(Al)电极的其他区域也将熔化,这将对衬底上已有的线路或电路产生不利的影响。
发明内容
技术问题:
为了解决上述问题,本发明的一个目的是提供一种在不影响两个半导体衬底上所形成电路的低温下使两个半导体衬底上形成的铝(Al)电极接合的方法,并且该方法不会对半导体制造设备造成污染。
技术方案:
根据本发明的一个方面,提供了一种用于使两个半导体衬底的铝(Al)电极接合的方法,包括:(a)分别在两个半导体衬底上形成铝(Al)电极,并在铝(Al)电极上沉积包含铝(Al)和铜(Cu)的金属合金;(b)使两个半导体衬底的铝(Al)电极面对面排列;(c)在低于已沉积的金属合金熔点的温度下对铝(Al)电极进行加热,并且在两个半导体衬底上施加一定的压力。
在本发明中,金属合金可以是Al0.83Cu0.17合金。
附图说明
图1至图3示出了根据本发明的实施方案使在两个半导体衬底上形成的铝(Al)电极接合的工艺。
具体实施方式
以下将结合附图对本发明进行详细描述。
图1至图3示出了根据本发明的实施方案使在两个半导体衬底上形成的铝(Al)电极接合的工艺。
图1示出了在两个半导体衬底上形成的铝(Al)电极。
待接合的铝(Al)电极13和23在半导体衬底10和20上形成,并且在其上沉积Al0.83Cu0.17合金15和25。
图2示出了使半导体衬底上的铝(Al)电极接合的工艺。
在待接合的铝(Al)电极13和23彼此搭接的情况下,以低于Al0.83Cu0.17合金15和25熔点的温度对半导体衬底10和20进行加热,并且向半导体衬底10和20上施加一定的压力。
由于施加在半导体衬底10和20上的压力,待接合的铝(Al)电极13和23受压,并因此使Al0.83Cu0.17合金15和25在低于Al0.83Cu0.17合金15和25在大气压下的熔点的温度熔化。
Al0.83Cu0.17合金15和25的熔点约为540℃,此温度远低于铝(Al)电极13和23的熔点650℃,因此适合于熔接。铝(Al)和铜(Cu)在Al0.83Cu0.17合金15和25中均匀混合。
图3示出了半导体衬底上铝(Al)电极的接合。
当在铝(Al)电极13和23上沉积Al0.83Cu0.17合金15和25,然后加热时,Al0.83Cu0.17合金15和25沉积的区域比铝(Al)电极13和23的区域熔化得快,从而防止在接合部分之外的区域的热损坏。
此外,由于在该制造工艺中应用了典型的合金金属,如铝(Al)和铜(Cu),所以在该半导体制造工艺中不会产生污染。来自在高温下涂覆至铝(Al)电极的合金的铜(Cu)扩散使Al电极的熔点降低,但由于由此扩散形成的合金的熔点比原合金的熔点高,所以对接合的影响并不明显。
尽管结合本发明的示例性实施方案对本发明进行了具体地表述与描述,但本领域技术人员可以理解,可在不脱离所附权利要求所限定的本发明精神和范围的情况下,对本发明进行各种形式上和细节的变化。
工业适用性
因此,在本发明中,可在低于Al0.83Cu0.17合金熔点的温度完成接合,而不对两个半导体衬底上形成的电路产生影响,并且接合可在施加压力的区域内选择性地完成。
Claims (3)
1.一种用于使两个半导体衬底的铝(Al)电极接合的方法,包括:
(a)分别在所述两个半导体衬底上形成铝(Al)电极,并在所述铝(Al)电极上沉积包含铝(Al)和铜(Cu)的金属合金;
(b)使所述两个半导体衬底的所述铝(Al)电极面对面排列;并且
(c)在低于已沉积的所述金属合金熔点的温度下对所述铝(Al)电极进行加热,并且在所述两个半导体衬底上施加一定的压力。
2.如权利要求1所述的方法,其中所述金属合金为Al0.83Cu0.17合金。
3.如权利要求1所述的方法,其中步骤(c)中的所述温度低于约540℃。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050017955 | 2005-03-04 | ||
KR1020050017955A KR100591461B1 (ko) | 2005-03-04 | 2005-03-04 | 두 반도체 기판의 알루미늄 전극 접합방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101133486A true CN101133486A (zh) | 2008-02-27 |
CN100508151C CN100508151C (zh) | 2009-07-01 |
Family
ID=36941400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2006800066816A Expired - Fee Related CN100508151C (zh) | 2005-03-04 | 2006-03-02 | 使两个半导体衬底的铝电极接合的方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7732300B2 (zh) |
EP (1) | EP1854135A4 (zh) |
JP (1) | JP2008530816A (zh) |
KR (1) | KR100591461B1 (zh) |
CN (1) | CN100508151C (zh) |
WO (1) | WO2006093386A1 (zh) |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4890784A (en) * | 1983-03-28 | 1990-01-02 | Rockwell International Corporation | Method for diffusion bonding aluminum |
US4854495A (en) * | 1986-06-20 | 1989-08-08 | Hitachi, Ltd. | Sealing structure, method of soldering and process for preparing sealing structure |
JPS63107127A (ja) * | 1986-10-24 | 1988-05-12 | Hitachi Ltd | 半導体装置 |
JP2835145B2 (ja) * | 1990-05-28 | 1998-12-14 | 株式会社東芝 | 電子装置 |
US5249732A (en) * | 1993-02-09 | 1993-10-05 | National Semiconductor Corp. | Method of bonding semiconductor chips to a substrate |
JPH06333983A (ja) * | 1993-05-19 | 1994-12-02 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
WO1998009332A1 (en) * | 1996-08-27 | 1998-03-05 | Nippon Steel Corporation | Semiconductor device provided with low melting point metal bumps and process for producing same |
JP3252745B2 (ja) * | 1997-03-31 | 2002-02-04 | 関西日本電気株式会社 | 半導体装置およびその製造方法 |
JP4033968B2 (ja) * | 1998-03-31 | 2008-01-16 | 新日鉄マテリアルズ株式会社 | 複数チップ混載型半導体装置 |
DE60037069T2 (de) * | 1999-05-28 | 2008-09-11 | Denki Kagaku Kogyo K.K. | Schaltung mit Substrat |
KR100347762B1 (ko) * | 1999-12-15 | 2002-08-09 | 엘지전자주식회사 | 베어칩 반도체 집적회로 및 회로기판 패턴의 직접 접합 방법 |
JP2002111182A (ja) * | 2000-09-29 | 2002-04-12 | Katsuaki Suganuma | 導電性接着剤で接続した部品の易剥離法 |
JP3735526B2 (ja) * | 2000-10-04 | 2006-01-18 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2003163458A (ja) * | 2001-11-29 | 2003-06-06 | Fujitsu Ltd | 多層配線基板及びその製造方法 |
KR20030047085A (ko) * | 2001-12-07 | 2003-06-18 | 엘지전선 주식회사 | 니켈 금속을 연결수단으로 이용한 전자부품 및 접속방법 |
US7098072B2 (en) * | 2002-03-01 | 2006-08-29 | Agng, Llc | Fluxless assembly of chip size semiconductor packages |
EP1403923A1 (en) * | 2002-09-27 | 2004-03-31 | Abb Research Ltd. | Press pack power semiconductor module |
JP2004288768A (ja) * | 2003-03-20 | 2004-10-14 | Mitsubishi Electric Corp | 多層配線基体の製造方法 |
US20060292823A1 (en) * | 2005-06-28 | 2006-12-28 | Shriram Ramanathan | Method and apparatus for bonding wafers |
-
2005
- 2005-03-04 KR KR1020050017955A patent/KR100591461B1/ko active IP Right Grant
-
2006
- 2006-03-02 JP JP2007556090A patent/JP2008530816A/ja active Pending
- 2006-03-02 CN CNB2006800066816A patent/CN100508151C/zh not_active Expired - Fee Related
- 2006-03-02 US US11/817,761 patent/US7732300B2/en active Active
- 2006-03-02 EP EP06716162A patent/EP1854135A4/en not_active Withdrawn
- 2006-03-02 WO PCT/KR2006/000712 patent/WO2006093386A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
EP1854135A1 (en) | 2007-11-14 |
EP1854135A4 (en) | 2012-05-02 |
CN100508151C (zh) | 2009-07-01 |
US20080293184A1 (en) | 2008-11-27 |
US7732300B2 (en) | 2010-06-08 |
WO2006093386A1 (en) | 2006-09-08 |
JP2008530816A (ja) | 2008-08-07 |
KR100591461B1 (ko) | 2006-06-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1066578C (zh) | 用于将集成电路芯片焊到芯片载体上的倒装片法 | |
EP0006810A1 (fr) | Procédé de fabrication d'un circuit intégré hybride | |
WO1997018584A1 (fr) | Procede de formation de bosse de contact sur un dispositif a semi-conducteurs | |
US20180050404A1 (en) | Method for forming a bonded joint | |
US8853002B2 (en) | Methods for metal bump die assembly | |
CN108807322A (zh) | 封装结构及其制造方法 | |
WO2016123957A1 (zh) | 封装方法、显示面板及显示装置 | |
CN116705867A (zh) | 无主栅太阳能电池及其制备方法 | |
CN108289390A (zh) | 解决小型阻容元件立碑的载板设计、封装方法及载板 | |
CN100508151C (zh) | 使两个半导体衬底的铝电极接合的方法 | |
CN106552990A (zh) | 一种贴片电位器的内部微焊接方法 | |
CN102245498A (zh) | 具有slid粘结连接的两个衬底的装置和用于制造这种装置的方法 | |
CN105397226A (zh) | 一种电热基板不镀镍钎焊工艺 | |
JPH02144821A (ja) | ヒューズ形成方法 | |
CN101234443B (zh) | 高尔夫球杆头的接合方法 | |
JPH06267963A (ja) | 半導体部品におけるバンプ電極の形成方法 | |
CN113141724B (zh) | 一种pcb印制电路板制作工艺 | |
US6509207B1 (en) | Soldering method and apparatus for a chip and electronic devices | |
JPS5911635A (ja) | 金属コ−テイング膜の製造方法 | |
JPS61113245A (ja) | 半導体装置の製造方法 | |
JP2005191200A (ja) | 太陽電池素子接続用インナーリード及び太陽電池モジュール並びに太陽電池モジュールの製造方法 | |
JPH1174448A (ja) | 素子搭載用基板、電子部品およびその製造方法 | |
JP2011233890A (ja) | レーザ焼結下板を有する基板 | |
JPS63293927A (ja) | 半導体装置の製造方法 | |
JPH06125162A (ja) | セラミックス配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090701 Termination date: 20140302 |