JP2008525933A - フローティングゲート間の結合効果を低減させたnand形−eeprom - Google Patents
フローティングゲート間の結合効果を低減させたnand形−eeprom Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Abstract
【選択図】図6B
Description
Claims (28)
- 不揮発性メモリの動作方法であって、
1組の不揮発性記憶要素のスレショールド電圧をゼロボルト未満の第1範囲に変換することによって前記不揮発性記憶要素を消去する消去工程と、
前記スレショールド電圧を圧縮して、ゼロボルトよりも高い第2範囲に変換する変換工程と、
前記第2範囲における少なくとも1部分の前記不揮発性記憶要素を、ゼロボルトよりも高い一又は複数の追加範囲に書込む書込み工程と、
を備えていることを特徴とする方法。 - 前記第1範囲は有効データ範囲ではなく、
ゼロボルトよりも高い前記第2範囲と前記追加範囲は有効データ範囲であることを特徴とする請求項1に記載の方法。 - 前記圧縮の後に、1部分の前記不揮発性記憶要素の書込み命令を受信する工程をさらに備えており、
少なくとも1部分の前記不揮発性記憶要素を書込む書込み工程は、前記書込み命令に応答して実行されることを特徴とする請求項1に記載の方法。 - 前記圧縮の前に、1部分の前記不揮発性記憶要素の書込み命令を受信する工程をさらに備えており、
前記少なくとも1部分の不揮発性記憶要素を書込む書込み工程と前記圧縮とが、前記書込み命令に応答して実行されることを特徴とする請求項1に記載の方法。 - 前記変換工程は、前記スレショールド電圧を8個の有効データ状態のうち一番目の有効データ状態へ変換する工程を含み、
前記書込み工程は、1部分の前記不揮発性記憶要素の前記スレショールド電圧を、二番目の有効データ状態、三番目の有効データ状態、四番目の有効データ状態、五番目の有効データ状態、六番目の有効データ状態、七番目の有効データ状態、八番目の有効データ状態のうちいずれか1つの有効データ状態へ変換する工程を含むことを特徴とする請求項1に記載の方法。 - 前記消去工程の前に、前記不揮発性記憶要素を書込む工程をさらに備えていることを特徴とする請求項1に記載の方法。
- 前記消去工程は、前記不揮発性記憶要素のフローティングゲートから電荷を除去する工程を含み、
前記圧縮及び前記変換工程は、前記不揮発性記憶要素のフローティングゲートに電荷を追加する工程を含むことを特徴とする請求項1に記載の方法。 - 前記不揮発性記憶要素はマルチ状態NAND形フラッシュメモリ要素であることを特徴とする請求項1に記載の方法。
- 前記不揮発性記憶要素はマルチ状態フラッシュメモリ要素であることを特徴とする請求項1に記載の方法。
- 前記不揮発性記憶要素の各々は複数のページにデータを記憶することを特徴とする請求項9に記載の方法。
- 前記不揮発性記憶要素の各々はデータを複数のページに記憶し、
前記書込み工程は、先行ページの隣接した不揮発性記憶要素にデータの書込みを行った後に、特定のページに関連した特定の不揮発性記憶要素にデータを書込む工程を含むことを特徴とする請求項9に記載の方法。 - 不揮発性メモリシステムであって、
複数の不揮発性記憶要素と、
前記不揮発性記憶要素を制御する一又は複数の制御回路とを備えており、
前記一又は複数の制御回路は、前記不揮発性記憶要素のスレショールド電圧をゼロボルト未満のレベルにまで低下させることによって前記不揮発性記憶要素を消去し、かつ前記スレショールド電圧を圧縮してゼロボルトよりも高いレベルにまで上昇させるとともに少なくとも1部分の前記不揮発性記憶要素をゼロボルトよりも高いレベルから一又は複数の有効データ状態に書込むことを特徴とする不揮発性メモリシステム。 - 前記ゼロボルト未満のレベルは有効データ範囲を含まず、
前記ゼロボルトよりも高いレベルは有効データ範囲を含むことを特徴とする請求項12に記載の不揮発性メモリシステム。 - 少なくとも1つのサブセットの前記不揮発性記憶要素を書込む前記書込みと前記圧縮とは、書込み命令に応答して実行されることを特徴とする請求項12に記載の不揮発性メモリシステム。
- 前記不揮発性記憶要素はマルチ状態NAND形フラッシュメモリ要素であることを特徴とする請求項12に記載の不揮発性メモリシステム。
- 前記不揮発性記憶要素の各々はデータを複数ページに記憶し、
前記一又は複数の制御回路は、先行ページの隣接した不揮発性記憶要素の書込みを行った後に、特定のページに関連した特定の不揮発性記憶要素を書込むことによって1部分の不揮発性記憶要素の書込みを行うことを特徴とする請求項15に記載の不揮発性メモリシステム。 - 不揮発性メモリの動作方法であって、
不揮発性記憶要素のスレショールド電圧を無効データに関連した第1範囲に変換することによって前記不揮発性記憶要素を消去する消去工程と、
前記不揮発性記憶要素の前記スレショールド電圧を、前記第1範囲とは異なる第2範囲に変換する変換工程と、
前記第2範囲からの少なくとも1部分の不揮発性記憶要素を、有効データ状態に関連した一又は複数の別の範囲に書込む書込み工程と、
を備えていることを特徴とする方法。 - 前記変換工程の後に書込み命令を受信する工程をさらに備えており、
少なくとも1サブセットの前記不揮発性記憶要素を書込む前記書込み工程は、前記書込み命令に応答して実行されることを特徴とする請求項17に記載の方法。 - 前記変換工程の前に書込み命令を受信する工程をさらに備えており、
少なくとも1サブセットの前記不揮発性記憶要素を書込む前記書込み工程と前記変換工程とは、前記書込み命令に応答して実行されることを特徴とする請求項17に記載の方法。 - 前記消去工程の前に、前記不揮発性記憶要素を書込む工程をさらに備えることを特徴とする請求項17に記載の方法。
- 前記不揮発性記憶要素はマルチ状態NAND形フラッシュメモリ要素であることを特徴とする請求項17に記載の方法。
- 前記不揮発性記憶要素の各々はデータを複数のページに分けて記憶し、
前記書込み工程は、先行ページの隣接した不揮発性記憶要素への書込み工程の後に、特定のページに関連した特定の不揮発性記憶要素に書込みを行う工程を含むことを特徴とする請求項21に記載の方法。 - 不揮発性記憶メモリシステムであって、
複数の不揮発性記憶要素と、
前記不揮発性記憶要素と通信した一又は複数の制御回路とを備えており、
前記一又は複数の制御回路は、1組の不揮発性記憶要素を前記不揮発性記憶要素のスレショールド電圧を有効データ範囲から無効データ範囲へ変換することにより消去し、かつ前記スレショールド電圧を圧縮して前記有効データ範囲の第1範囲へ変換して少なくとも1部分の不揮発性記憶要素を前記有効範囲の第1範囲から前記有効範囲の一又は複数の追加の範囲へ変換することを特徴とする不揮発性メモリシステム。 - 前記不揮発性記憶要素はマルチ状態NAND形フラッシュメモリ要素であることを特徴とする請求項23に記載の不揮発性メモリシステム。
- 不揮発性メモリを消去する方法であって、
1組の不揮発性記憶要素を、前記不揮発性記憶要素のスレショールド電圧を有効データ範囲外の範囲へ意図的に変換することによって消去する消去工程と、
前記スレショールド電圧を圧縮し、前記スレショールド電圧を有効データ範囲に変換する工程と、
を備えていることを特徴とする方法。 - 前記消去工程は、前記不揮発性記憶要素のスレショールド電圧が低下し、有効データを示すために用いた範囲よりも低いスレショールド電圧分布が形成されるように、前記不揮発性記憶要素に消去パルスを印加する工程を含み、
前記圧縮工程は、前記不揮発性記憶要素のスレショールド電圧を有効データ状態を示す範囲に上昇させる工程を含むことを特徴とする請求項25に記載の方法。 - 前記スレショールド電圧分布はゼロボルト未満であり、
前記有効データ状態はゼロボルトよりも高いことを特徴とする請求項26に記載の方法。 - 前記不揮発性記憶要素はマルチ状態NAND形フラッシュメモリ要素であることを特徴とする請求項27に記載の方法。
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US11/021,872 US7230851B2 (en) | 2004-12-23 | 2004-12-23 | Reducing floating gate to floating gate coupling effect |
PCT/US2005/045339 WO2006071541A1 (en) | 2004-12-23 | 2005-12-15 | Nand-eeprom with reduction of floating gate to floating gate coupling effect |
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US (2) | US7230851B2 (ja) |
EP (1) | EP1829046A1 (ja) |
JP (1) | JP2008525933A (ja) |
KR (1) | KR100868805B1 (ja) |
CN (1) | CN101095197B (ja) |
TW (1) | TWI308337B (ja) |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011159364A (ja) * | 2010-02-02 | 2011-08-18 | Toshiba Corp | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の駆動方法 |
WO2012039511A1 (en) * | 2010-09-24 | 2012-03-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP2012160236A (ja) * | 2011-02-01 | 2012-08-23 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8345484B2 (en) | 2009-08-24 | 2013-01-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and system, and method of programming a nonvolatile memory device |
JP2013073639A (ja) * | 2011-09-27 | 2013-04-22 | Lapis Semiconductor Co Ltd | 半導体不揮発性メモリ及びデータ書き込み方法 |
JP2013131275A (ja) * | 2011-12-22 | 2013-07-04 | Toshiba Corp | 不揮発性半導体記憶装置 |
Families Citing this family (243)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7230851B2 (en) * | 2004-12-23 | 2007-06-12 | Sandisk Corporation | Reducing floating gate to floating gate coupling effect |
US7450433B2 (en) * | 2004-12-29 | 2008-11-11 | Sandisk Corporation | Word line compensation in non-volatile memory erase operations |
US7251160B2 (en) * | 2005-03-16 | 2007-07-31 | Sandisk Corporation | Non-volatile memory and method with power-saving read and program-verify operations |
US7403424B2 (en) * | 2005-03-31 | 2008-07-22 | Sandisk Corporation | Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells |
US7193898B2 (en) * | 2005-06-20 | 2007-03-20 | Sandisk Corporation | Compensation currents in non-volatile memory read operations |
WO2007132456A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
KR101202537B1 (ko) | 2006-05-12 | 2012-11-19 | 애플 인크. | 메모리 디바이스를 위한 결합된 왜곡 추정 및 에러 보정 코딩 |
CN103280239B (zh) * | 2006-05-12 | 2016-04-06 | 苹果公司 | 存储设备中的失真估计和消除 |
KR100741466B1 (ko) * | 2006-05-22 | 2007-07-20 | 삼성전자주식회사 | 비휘발성 기억 장치의 동작 방법 |
US7495953B2 (en) * | 2006-07-20 | 2009-02-24 | Sandisk Corporation | System for configuring compensation |
US7400535B2 (en) * | 2006-07-20 | 2008-07-15 | Sandisk Corporation | System that compensates for coupling during programming |
US7506113B2 (en) * | 2006-07-20 | 2009-03-17 | Sandisk Corporation | Method for configuring compensation |
US7885119B2 (en) * | 2006-07-20 | 2011-02-08 | Sandisk Corporation | Compensating for coupling during programming |
US7522454B2 (en) * | 2006-07-20 | 2009-04-21 | Sandisk Corporation | Compensating for coupling based on sensing a neighbor using coupling |
US7443729B2 (en) * | 2006-07-20 | 2008-10-28 | Sandisk Corporation | System that compensates for coupling based on sensing a neighbor using coupling |
WO2008026203A2 (en) | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
US7734861B2 (en) | 2006-09-08 | 2010-06-08 | Sandisk Corporation | Pseudo random and command driven bit compensation for the cycling effects in flash memory |
US7885112B2 (en) * | 2007-09-07 | 2011-02-08 | Sandisk Corporation | Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages |
US7606966B2 (en) * | 2006-09-08 | 2009-10-20 | Sandisk Corporation | Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory |
US7911835B2 (en) * | 2006-10-04 | 2011-03-22 | Samsung Electronics Co., Ltd. | Programming and reading five bits of data in two non-volatile memory cells |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US8059456B2 (en) * | 2006-11-07 | 2011-11-15 | Sandisk Il Ltd. | Programming a NAND flash memory with reduced program disturb |
US7924648B2 (en) * | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7616501B2 (en) * | 2006-12-04 | 2009-11-10 | Semiconductor Components Industries, L.L.C. | Method for reducing charge loss in analog floating gate cell |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US7619930B2 (en) * | 2007-02-20 | 2009-11-17 | Sandisk Corporation | Dynamic verify based on threshold voltage distribution |
CN101715595A (zh) | 2007-03-12 | 2010-05-26 | 爱诺彼得技术有限责任公司 | 存储器单元读取阈的自适应估计 |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
WO2008139441A2 (en) * | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US7986553B2 (en) * | 2007-06-15 | 2011-07-26 | Micron Technology, Inc. | Programming of a solid state memory utilizing analog communication of bit patterns |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
WO2009050703A2 (en) | 2007-10-19 | 2009-04-23 | Anobit Technologies | Data storage in analog memory cell arrays having erase failures |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
KR101391881B1 (ko) * | 2007-10-23 | 2014-05-07 | 삼성전자주식회사 | 멀티-비트 플래시 메모리 장치 및 그것의 프로그램 및 읽기방법 |
WO2009063450A2 (en) | 2007-11-13 | 2009-05-22 | Anobit Technologies | Optimized selection of memory units in multi-unit memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) * | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
KR101506336B1 (ko) * | 2008-10-10 | 2015-03-27 | 삼성전자주식회사 | 산화막 복구 기능을 갖는 비휘발성 메모리 장치 그리고 그것의 블록 관리 방법 |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
KR101518039B1 (ko) * | 2008-12-08 | 2015-05-07 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법 |
US8397131B1 (en) | 2008-12-31 | 2013-03-12 | Apple Inc. | Efficient readout schemes for analog memory cell devices |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8023345B2 (en) * | 2009-02-24 | 2011-09-20 | International Business Machines Corporation | Iteratively writing contents to memory locations using a statistical model |
US8166368B2 (en) * | 2009-02-24 | 2012-04-24 | International Business Machines Corporation | Writing a special symbol to a memory to indicate the absence of a data signal |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US7978511B2 (en) | 2009-05-28 | 2011-07-12 | Micron Technology, Inc. | Data line management in a memory device |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8230276B2 (en) * | 2009-09-28 | 2012-07-24 | International Business Machines Corporation | Writing to memory using adaptive write techniques |
US8386739B2 (en) * | 2009-09-28 | 2013-02-26 | International Business Machines Corporation | Writing to memory using shared address buses |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8463985B2 (en) | 2010-03-31 | 2013-06-11 | International Business Machines Corporation | Constrained coding to reduce floating gate coupling in non-volatile memories |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
JP5330421B2 (ja) * | 2011-02-01 | 2013-10-30 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US8843693B2 (en) | 2011-05-17 | 2014-09-23 | SanDisk Technologies, Inc. | Non-volatile memory and method with improved data scrambling |
CN102347069B (zh) * | 2011-05-26 | 2013-04-03 | 忆正存储技术(武汉)有限公司 | 多层式存储闪存阵列的编程方式及其切换控制方法 |
US9171627B2 (en) | 2012-04-11 | 2015-10-27 | Aplus Flash Technology, Inc. | Non-boosting program inhibit scheme in NAND design |
US9087595B2 (en) | 2012-04-20 | 2015-07-21 | Aplus Flash Technology, Inc. | Shielding 2-cycle half-page read and program schemes for advanced NAND flash design |
US9001577B2 (en) | 2012-06-01 | 2015-04-07 | Micron Technology, Inc. | Memory cell sensing |
JP2013254537A (ja) * | 2012-06-06 | 2013-12-19 | Toshiba Corp | 半導体記憶装置及びコントローラ |
US9158667B2 (en) | 2013-03-04 | 2015-10-13 | Micron Technology, Inc. | Apparatuses and methods for performing logical operations using sensing circuitry |
CN104103317B (zh) * | 2013-04-12 | 2017-05-03 | 旺宏电子股份有限公司 | 非易失性存储器及其操作方法 |
US8879330B1 (en) * | 2013-04-30 | 2014-11-04 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) with variable verify operations |
US9183940B2 (en) | 2013-05-21 | 2015-11-10 | Aplus Flash Technology, Inc. | Low disturbance, power-consumption, and latency in NAND read and program-verify operations |
US9263137B2 (en) | 2013-06-27 | 2016-02-16 | Aplus Flash Technology, Inc. | NAND array architecture for multiple simutaneous program and read |
WO2015013689A2 (en) | 2013-07-25 | 2015-01-29 | Aplus Flash Technology, Inc. | Nand array hiarchical bl structures for multiple-wl and all -bl simultaneous erase, erase-verify, program, program-verify, and read operations |
US8964496B2 (en) | 2013-07-26 | 2015-02-24 | Micron Technology, Inc. | Apparatuses and methods for performing compare operations using sensing circuitry |
US8971124B1 (en) | 2013-08-08 | 2015-03-03 | Micron Technology, Inc. | Apparatuses and methods for performing logical operations using sensing circuitry |
US9153305B2 (en) | 2013-08-30 | 2015-10-06 | Micron Technology, Inc. | Independently addressable memory array address spaces |
US9293205B2 (en) | 2013-09-14 | 2016-03-22 | Aplus Flash Technology, Inc | Multi-task concurrent/pipeline NAND operations on all planes |
US9019785B2 (en) | 2013-09-19 | 2015-04-28 | Micron Technology, Inc. | Data shifting via a number of isolation devices |
US9449675B2 (en) | 2013-10-31 | 2016-09-20 | Micron Technology, Inc. | Apparatuses and methods for identifying an extremum value stored in an array of memory cells |
US9430191B2 (en) | 2013-11-08 | 2016-08-30 | Micron Technology, Inc. | Division operations for memory |
WO2015100434A2 (en) | 2013-12-25 | 2015-07-02 | Aplus Flash Technology, Inc | A HYBRID NAND WITH ALL-BL m-PAGE OPERATION SCHEME |
JP6262063B2 (ja) * | 2014-03-18 | 2018-01-17 | 東芝メモリ株式会社 | 不揮発性メモリおよび書き込み方法 |
US9934856B2 (en) | 2014-03-31 | 2018-04-03 | Micron Technology, Inc. | Apparatuses and methods for comparing data patterns in memory |
US10074407B2 (en) | 2014-06-05 | 2018-09-11 | Micron Technology, Inc. | Apparatuses and methods for performing invert operations using sensing circuitry |
US9449674B2 (en) | 2014-06-05 | 2016-09-20 | Micron Technology, Inc. | Performing logical operations using sensing circuitry |
US9704540B2 (en) | 2014-06-05 | 2017-07-11 | Micron Technology, Inc. | Apparatuses and methods for parity determination using sensing circuitry |
US9455020B2 (en) | 2014-06-05 | 2016-09-27 | Micron Technology, Inc. | Apparatuses and methods for performing an exclusive or operation using sensing circuitry |
US9496023B2 (en) | 2014-06-05 | 2016-11-15 | Micron Technology, Inc. | Comparison operations on logical representations of values in memory |
US9711207B2 (en) | 2014-06-05 | 2017-07-18 | Micron Technology, Inc. | Performing logical operations using sensing circuitry |
US9786335B2 (en) | 2014-06-05 | 2017-10-10 | Micron Technology, Inc. | Apparatuses and methods for performing logical operations using sensing circuitry |
US9830999B2 (en) | 2014-06-05 | 2017-11-28 | Micron Technology, Inc. | Comparison operations in memory |
US9779019B2 (en) | 2014-06-05 | 2017-10-03 | Micron Technology, Inc. | Data storage layout |
US9910787B2 (en) | 2014-06-05 | 2018-03-06 | Micron Technology, Inc. | Virtual address table |
US9711206B2 (en) | 2014-06-05 | 2017-07-18 | Micron Technology, Inc. | Performing logical operations using sensing circuitry |
US9659636B2 (en) | 2014-07-22 | 2017-05-23 | Peter Wung Lee | NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations |
US9904515B2 (en) | 2014-09-03 | 2018-02-27 | Micron Technology, Inc. | Multiplication operations in memory |
US9589602B2 (en) | 2014-09-03 | 2017-03-07 | Micron Technology, Inc. | Comparison operations in memory |
US10068652B2 (en) | 2014-09-03 | 2018-09-04 | Micron Technology, Inc. | Apparatuses and methods for determining population count |
US9898252B2 (en) | 2014-09-03 | 2018-02-20 | Micron Technology, Inc. | Multiplication operations in memory |
US9847110B2 (en) | 2014-09-03 | 2017-12-19 | Micron Technology, Inc. | Apparatuses and methods for storing a data value in multiple columns of an array corresponding to digits of a vector |
US9740607B2 (en) | 2014-09-03 | 2017-08-22 | Micron Technology, Inc. | Swap operations in memory |
US9747961B2 (en) | 2014-09-03 | 2017-08-29 | Micron Technology, Inc. | Division operations in memory |
US9836218B2 (en) | 2014-10-03 | 2017-12-05 | Micron Technology, Inc. | Computing reduction and prefix sum operations in memory |
US9940026B2 (en) | 2014-10-03 | 2018-04-10 | Micron Technology, Inc. | Multidimensional contiguous memory allocation |
US10163467B2 (en) | 2014-10-16 | 2018-12-25 | Micron Technology, Inc. | Multiple endianness compatibility |
US10147480B2 (en) | 2014-10-24 | 2018-12-04 | Micron Technology, Inc. | Sort operation in memory |
US9779784B2 (en) | 2014-10-29 | 2017-10-03 | Micron Technology, Inc. | Apparatuses and methods for performing logical operations using sensing circuitry |
US10073635B2 (en) | 2014-12-01 | 2018-09-11 | Micron Technology, Inc. | Multiple endianness compatibility |
US9747960B2 (en) | 2014-12-01 | 2017-08-29 | Micron Technology, Inc. | Apparatuses and methods for converting a mask to an index |
US10061590B2 (en) | 2015-01-07 | 2018-08-28 | Micron Technology, Inc. | Generating and executing a control flow |
US10032493B2 (en) | 2015-01-07 | 2018-07-24 | Micron Technology, Inc. | Longest element length determination in memory |
US9583163B2 (en) | 2015-02-03 | 2017-02-28 | Micron Technology, Inc. | Loop structure for operations in memory |
EP3254286B1 (en) | 2015-02-06 | 2019-09-11 | Micron Technology, INC. | Apparatuses and methods for parallel writing to multiple memory device locations |
EP3254287A4 (en) | 2015-02-06 | 2018-08-08 | Micron Technology, INC. | Apparatuses and methods for memory device as a store for program instructions |
WO2016126472A1 (en) | 2015-02-06 | 2016-08-11 | Micron Technology, Inc. | Apparatuses and methods for scatter and gather |
US10522212B2 (en) | 2015-03-10 | 2019-12-31 | Micron Technology, Inc. | Apparatuses and methods for shift decisions |
US9741399B2 (en) | 2015-03-11 | 2017-08-22 | Micron Technology, Inc. | Data shift by elements of a vector in memory |
US9898253B2 (en) | 2015-03-11 | 2018-02-20 | Micron Technology, Inc. | Division operations on variable length elements in memory |
EP3268965A4 (en) | 2015-03-12 | 2018-10-03 | Micron Technology, INC. | Apparatuses and methods for data movement |
US10146537B2 (en) | 2015-03-13 | 2018-12-04 | Micron Technology, Inc. | Vector population count determination in memory |
US10049054B2 (en) | 2015-04-01 | 2018-08-14 | Micron Technology, Inc. | Virtual register file |
US10140104B2 (en) | 2015-04-14 | 2018-11-27 | Micron Technology, Inc. | Target architecture determination |
US9959923B2 (en) | 2015-04-16 | 2018-05-01 | Micron Technology, Inc. | Apparatuses and methods to reverse data stored in memory |
US10073786B2 (en) | 2015-05-28 | 2018-09-11 | Micron Technology, Inc. | Apparatuses and methods for compute enabled cache |
US9704541B2 (en) | 2015-06-12 | 2017-07-11 | Micron Technology, Inc. | Simulating access lines |
US9921777B2 (en) | 2015-06-22 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for data transfer from sensing circuitry to a controller |
US9996479B2 (en) | 2015-08-17 | 2018-06-12 | Micron Technology, Inc. | Encryption of executables in computational memory |
US9905276B2 (en) | 2015-12-21 | 2018-02-27 | Micron Technology, Inc. | Control of sensing components in association with performing operations |
US9952925B2 (en) | 2016-01-06 | 2018-04-24 | Micron Technology, Inc. | Error code calculation on sensing circuitry |
US10048888B2 (en) | 2016-02-10 | 2018-08-14 | Micron Technology, Inc. | Apparatuses and methods for partitioned parallel data movement |
US9892767B2 (en) | 2016-02-12 | 2018-02-13 | Micron Technology, Inc. | Data gathering in memory |
US9971541B2 (en) | 2016-02-17 | 2018-05-15 | Micron Technology, Inc. | Apparatuses and methods for data movement |
US10956439B2 (en) | 2016-02-19 | 2021-03-23 | Micron Technology, Inc. | Data transfer with a bit vector operation device |
US9899070B2 (en) | 2016-02-19 | 2018-02-20 | Micron Technology, Inc. | Modified decode for corner turn |
US9697876B1 (en) | 2016-03-01 | 2017-07-04 | Micron Technology, Inc. | Vertical bit vector shift in memory |
US10262721B2 (en) | 2016-03-10 | 2019-04-16 | Micron Technology, Inc. | Apparatuses and methods for cache invalidate |
US9997232B2 (en) | 2016-03-10 | 2018-06-12 | Micron Technology, Inc. | Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations |
US10379772B2 (en) | 2016-03-16 | 2019-08-13 | Micron Technology, Inc. | Apparatuses and methods for operations using compressed and decompressed data |
US9910637B2 (en) | 2016-03-17 | 2018-03-06 | Micron Technology, Inc. | Signed division in memory |
US11074988B2 (en) | 2016-03-22 | 2021-07-27 | Micron Technology, Inc. | Apparatus and methods for debugging on a host and memory device |
US10120740B2 (en) | 2016-03-22 | 2018-11-06 | Micron Technology, Inc. | Apparatus and methods for debugging on a memory device |
US10388393B2 (en) | 2016-03-22 | 2019-08-20 | Micron Technology, Inc. | Apparatus and methods for debugging on a host and memory device |
US10977033B2 (en) | 2016-03-25 | 2021-04-13 | Micron Technology, Inc. | Mask patterns generated in memory from seed vectors |
US10474581B2 (en) | 2016-03-25 | 2019-11-12 | Micron Technology, Inc. | Apparatuses and methods for cache operations |
US10074416B2 (en) | 2016-03-28 | 2018-09-11 | Micron Technology, Inc. | Apparatuses and methods for data movement |
US10430244B2 (en) | 2016-03-28 | 2019-10-01 | Micron Technology, Inc. | Apparatuses and methods to determine timing of operations |
US10453502B2 (en) | 2016-04-04 | 2019-10-22 | Micron Technology, Inc. | Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions |
US10607665B2 (en) | 2016-04-07 | 2020-03-31 | Micron Technology, Inc. | Span mask generation |
US9818459B2 (en) | 2016-04-19 | 2017-11-14 | Micron Technology, Inc. | Invert operations using sensing circuitry |
US10153008B2 (en) | 2016-04-20 | 2018-12-11 | Micron Technology, Inc. | Apparatuses and methods for performing corner turn operations using sensing circuitry |
US9659605B1 (en) | 2016-04-20 | 2017-05-23 | Micron Technology, Inc. | Apparatuses and methods for performing corner turn operations using sensing circuitry |
US10042608B2 (en) | 2016-05-11 | 2018-08-07 | Micron Technology, Inc. | Signed division in memory |
US9659610B1 (en) | 2016-05-18 | 2017-05-23 | Micron Technology, Inc. | Apparatuses and methods for shifting data |
US10049707B2 (en) | 2016-06-03 | 2018-08-14 | Micron Technology, Inc. | Shifting data |
US10387046B2 (en) | 2016-06-22 | 2019-08-20 | Micron Technology, Inc. | Bank to bank data transfer |
US10037785B2 (en) | 2016-07-08 | 2018-07-31 | Micron Technology, Inc. | Scan chain operation in sensing circuitry |
US10388360B2 (en) | 2016-07-19 | 2019-08-20 | Micron Technology, Inc. | Utilization of data stored in an edge section of an array |
US10733089B2 (en) | 2016-07-20 | 2020-08-04 | Micron Technology, Inc. | Apparatuses and methods for write address tracking |
US10387299B2 (en) | 2016-07-20 | 2019-08-20 | Micron Technology, Inc. | Apparatuses and methods for transferring data |
US9972367B2 (en) | 2016-07-21 | 2018-05-15 | Micron Technology, Inc. | Shifting data in sensing circuitry |
US9767864B1 (en) | 2016-07-21 | 2017-09-19 | Micron Technology, Inc. | Apparatuses and methods for storing a data value in a sensing circuitry element |
US10303632B2 (en) | 2016-07-26 | 2019-05-28 | Micron Technology, Inc. | Accessing status information |
US10468087B2 (en) | 2016-07-28 | 2019-11-05 | Micron Technology, Inc. | Apparatuses and methods for operations in a self-refresh state |
US9990181B2 (en) | 2016-08-03 | 2018-06-05 | Micron Technology, Inc. | Apparatuses and methods for random number generation |
US11029951B2 (en) | 2016-08-15 | 2021-06-08 | Micron Technology, Inc. | Smallest or largest value element determination |
US10606587B2 (en) | 2016-08-24 | 2020-03-31 | Micron Technology, Inc. | Apparatus and methods related to microcode instructions indicating instruction types |
US10466928B2 (en) | 2016-09-15 | 2019-11-05 | Micron Technology, Inc. | Updating a register in memory |
US10387058B2 (en) | 2016-09-29 | 2019-08-20 | Micron Technology, Inc. | Apparatuses and methods to change data category values |
US10014034B2 (en) | 2016-10-06 | 2018-07-03 | Micron Technology, Inc. | Shifting data in sensing circuitry |
US10529409B2 (en) | 2016-10-13 | 2020-01-07 | Micron Technology, Inc. | Apparatuses and methods to perform logical operations using sensing circuitry |
US9805772B1 (en) | 2016-10-20 | 2017-10-31 | Micron Technology, Inc. | Apparatuses and methods to selectively perform logical operations |
CN207637499U (zh) | 2016-11-08 | 2018-07-20 | 美光科技公司 | 用于形成在存储器单元阵列上方的计算组件的设备 |
US10423353B2 (en) | 2016-11-11 | 2019-09-24 | Micron Technology, Inc. | Apparatuses and methods for memory alignment |
US9761300B1 (en) | 2016-11-22 | 2017-09-12 | Micron Technology, Inc. | Data shift apparatuses and methods |
US10402340B2 (en) | 2017-02-21 | 2019-09-03 | Micron Technology, Inc. | Memory array page table walk |
US10403352B2 (en) | 2017-02-22 | 2019-09-03 | Micron Technology, Inc. | Apparatuses and methods for compute in data path |
US10268389B2 (en) | 2017-02-22 | 2019-04-23 | Micron Technology, Inc. | Apparatuses and methods for in-memory operations |
US10838899B2 (en) | 2017-03-21 | 2020-11-17 | Micron Technology, Inc. | Apparatuses and methods for in-memory data switching networks |
US10185674B2 (en) | 2017-03-22 | 2019-01-22 | Micron Technology, Inc. | Apparatus and methods for in data path compute operations |
US11222260B2 (en) | 2017-03-22 | 2022-01-11 | Micron Technology, Inc. | Apparatuses and methods for operating neural networks |
US10049721B1 (en) | 2017-03-27 | 2018-08-14 | Micron Technology, Inc. | Apparatuses and methods for in-memory operations |
US10147467B2 (en) | 2017-04-17 | 2018-12-04 | Micron Technology, Inc. | Element value comparison in memory |
US10043570B1 (en) | 2017-04-17 | 2018-08-07 | Micron Technology, Inc. | Signed element compare in memory |
US9997212B1 (en) | 2017-04-24 | 2018-06-12 | Micron Technology, Inc. | Accessing data in memory |
US10942843B2 (en) | 2017-04-25 | 2021-03-09 | Micron Technology, Inc. | Storing data elements of different lengths in respective adjacent rows or columns according to memory shapes |
US10236038B2 (en) | 2017-05-15 | 2019-03-19 | Micron Technology, Inc. | Bank to bank data transfer |
US10068664B1 (en) | 2017-05-19 | 2018-09-04 | Micron Technology, Inc. | Column repair in memory |
US10013197B1 (en) | 2017-06-01 | 2018-07-03 | Micron Technology, Inc. | Shift skip |
US10262701B2 (en) | 2017-06-07 | 2019-04-16 | Micron Technology, Inc. | Data transfer between subarrays in memory |
US10152271B1 (en) | 2017-06-07 | 2018-12-11 | Micron Technology, Inc. | Data replication |
US10318168B2 (en) | 2017-06-19 | 2019-06-11 | Micron Technology, Inc. | Apparatuses and methods for simultaneous in data path compute operations |
US10162005B1 (en) | 2017-08-09 | 2018-12-25 | Micron Technology, Inc. | Scan chain operations |
US10534553B2 (en) | 2017-08-30 | 2020-01-14 | Micron Technology, Inc. | Memory array accessibility |
US10346092B2 (en) | 2017-08-31 | 2019-07-09 | Micron Technology, Inc. | Apparatuses and methods for in-memory operations using timing circuitry |
US10416927B2 (en) | 2017-08-31 | 2019-09-17 | Micron Technology, Inc. | Processing in memory |
US10741239B2 (en) | 2017-08-31 | 2020-08-11 | Micron Technology, Inc. | Processing in memory device including a row address strobe manager |
US10409739B2 (en) | 2017-10-24 | 2019-09-10 | Micron Technology, Inc. | Command selection policy |
US10522210B2 (en) | 2017-12-14 | 2019-12-31 | Micron Technology, Inc. | Apparatuses and methods for subarray addressing |
US10332586B1 (en) | 2017-12-19 | 2019-06-25 | Micron Technology, Inc. | Apparatuses and methods for subrow addressing |
US10614875B2 (en) | 2018-01-30 | 2020-04-07 | Micron Technology, Inc. | Logical operations using memory cells |
US11194477B2 (en) | 2018-01-31 | 2021-12-07 | Micron Technology, Inc. | Determination of a match between data values stored by three or more arrays |
US10437557B2 (en) | 2018-01-31 | 2019-10-08 | Micron Technology, Inc. | Determination of a match between data values stored by several arrays |
US10725696B2 (en) | 2018-04-12 | 2020-07-28 | Micron Technology, Inc. | Command selection policy with read priority |
US10440341B1 (en) | 2018-06-07 | 2019-10-08 | Micron Technology, Inc. | Image processor formed in an array of memory cells |
US11175915B2 (en) | 2018-10-10 | 2021-11-16 | Micron Technology, Inc. | Vector registers implemented in memory |
US10769071B2 (en) | 2018-10-10 | 2020-09-08 | Micron Technology, Inc. | Coherent memory access |
US10483978B1 (en) | 2018-10-16 | 2019-11-19 | Micron Technology, Inc. | Memory device processing |
US11184446B2 (en) | 2018-12-05 | 2021-11-23 | Micron Technology, Inc. | Methods and apparatus for incentivizing participation in fog networks |
US10867655B1 (en) | 2019-07-08 | 2020-12-15 | Micron Technology, Inc. | Methods and apparatus for dynamically adjusting performance of partitioned memory |
US11360768B2 (en) | 2019-08-14 | 2022-06-14 | Micron Technolgy, Inc. | Bit string operations in memory |
US11449577B2 (en) | 2019-11-20 | 2022-09-20 | Micron Technology, Inc. | Methods and apparatus for performing video processing matrix operations within a memory array |
US11853385B2 (en) | 2019-12-05 | 2023-12-26 | Micron Technology, Inc. | Methods and apparatus for performing diversity matrix operations within a memory array |
US11227641B1 (en) | 2020-07-21 | 2022-01-18 | Micron Technology, Inc. | Arithmetic operations in memory |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05258583A (ja) * | 1992-03-02 | 1993-10-08 | Nec Corp | 不揮発性記憶装置の制御方法 |
JPH08102198A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 電気的書換え可能な不揮発性半導体記憶装置の初期化方 法 |
JPH09306185A (ja) * | 1996-05-17 | 1997-11-28 | Matsushita Electron Corp | 半導体記憶装置及びその駆動方法 |
JPH11177070A (ja) * | 1997-12-10 | 1999-07-02 | Sony Corp | 不揮発性半導体記憶装置及びその駆動方法 |
JP2000236031A (ja) * | 1999-02-16 | 2000-08-29 | Toshiba Corp | 不揮発性半導体記憶装置 |
WO2004109806A1 (ja) * | 2003-06-04 | 2004-12-16 | Fujitsu Limited | 不揮発性半導体メモリ |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132935A (en) * | 1990-04-16 | 1992-07-21 | Ashmore Jr Benjamin H | Erasure of eeprom memory arrays to prevent over-erased cells |
US5270979A (en) * | 1991-03-15 | 1993-12-14 | Sundisk Corporation | Method for optimum erasing of EEPROM |
US5680350A (en) * | 1994-12-14 | 1997-10-21 | Micron Technology, Inc. | Method for narrowing threshold voltage distribution in a block erased flash memory array |
US5576992A (en) * | 1995-08-30 | 1996-11-19 | Texas Instruments Incorporated | Extended-life method for soft-programming floating-gate memory cells |
US5937174A (en) * | 1996-06-28 | 1999-08-10 | Lsi Logic Corporation | Scalable hierarchial memory structure for high data bandwidth raid applications |
KR100323554B1 (ko) * | 1997-05-14 | 2002-03-08 | 니시무로 타이죠 | 불휘발성반도체메모리장치 |
US5912845A (en) * | 1997-09-10 | 1999-06-15 | Macronix International Co., Ltd. | Method and circuit for substrate current induced hot e- injection (SCIHE) approach for VT convergence at low VCC voltage |
US5930174A (en) * | 1997-12-11 | 1999-07-27 | Amic Technology, Inc. | Circuit and method for erasing flash memory array |
KR100257868B1 (ko) * | 1997-12-29 | 2000-06-01 | 윤종용 | 노어형 플래시 메모리 장치의 소거 방법 |
US6587903B2 (en) | 1998-02-27 | 2003-07-01 | Micron Technology, Inc. | Soft programming for recovery of overerasure |
US6172909B1 (en) * | 1999-08-09 | 2001-01-09 | Advanced Micro Devices, Inc. | Ramped gate technique for soft programming to tighten the Vt distribution |
US6288938B1 (en) * | 1999-08-19 | 2001-09-11 | Azalea Microelectronics Corporation | Flash memory architecture and method of operation |
US6252803B1 (en) * | 2000-10-23 | 2001-06-26 | Advanced Micro Devices, Inc. | Automatic program disturb with intelligent soft programming for flash cells |
US6456533B1 (en) * | 2001-02-28 | 2002-09-24 | Advanced Micro Devices, Inc. | Higher program VT and faster programming rates based on improved erase methods |
US6711056B2 (en) * | 2001-03-12 | 2004-03-23 | Micron Technology, Inc. | Memory with row redundancy |
US6438037B1 (en) | 2001-05-09 | 2002-08-20 | Advanced Micro Devices, Inc. | Threshold voltage compacting for non-volatile semiconductor memory designs |
US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
ITMI20011232A1 (it) * | 2001-06-12 | 2002-12-12 | St Microelectronics Srl | Metodo di riprogrammazione successiva ad una operazione di cancellazione di una matrice di celle di memoria non volatile, in particolare di |
US6522580B2 (en) * | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
JP3984445B2 (ja) * | 2001-09-12 | 2007-10-03 | シャープ株式会社 | 不揮発性半導体メモリ装置のオーバーイレースセル検出方法 |
US6684173B2 (en) * | 2001-10-09 | 2004-01-27 | Micron Technology, Inc. | System and method of testing non-volatile memory cells |
US6967872B2 (en) * | 2001-12-18 | 2005-11-22 | Sandisk Corporation | Method and system for programming and inhibiting multi-level, non-volatile memory cells |
KR100463197B1 (ko) * | 2001-12-24 | 2004-12-23 | 삼성전자주식회사 | 멀티-페이지 프로그램 동작, 멀티-페이지 읽기 동작,그리고 멀티-블록 소거 동작을 갖는 낸드 플래시 메모리장치 |
US6661711B2 (en) * | 2002-02-06 | 2003-12-09 | Sandisk Corporation | Implementation of an inhibit during soft programming to tighten an erase voltage distribution |
US6639844B1 (en) * | 2002-03-13 | 2003-10-28 | Advanced Micro Devices, Inc. | Overerase correction method |
US6657891B1 (en) * | 2002-11-29 | 2003-12-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device for storing multivalued data |
US6735114B1 (en) * | 2003-02-04 | 2004-05-11 | Advanced Micro Devices, Inc. | Method of improving dynamic reference tracking for flash memory unit |
KR100535651B1 (ko) * | 2003-06-30 | 2005-12-08 | 주식회사 하이닉스반도체 | 플래시 메모리 셀과, 낸드 및 노아 타입의 플래시 메모리장치의 독출방법 |
US7230851B2 (en) * | 2004-12-23 | 2007-06-12 | Sandisk Corporation | Reducing floating gate to floating gate coupling effect |
-
2004
- 2004-12-23 US US11/021,872 patent/US7230851B2/en not_active Expired - Fee Related
-
2005
- 2005-12-15 KR KR1020077014370A patent/KR100868805B1/ko not_active IP Right Cessation
- 2005-12-15 WO PCT/US2005/045339 patent/WO2006071541A1/en active Application Filing
- 2005-12-15 EP EP05854122A patent/EP1829046A1/en not_active Withdrawn
- 2005-12-15 JP JP2007548304A patent/JP2008525933A/ja active Pending
- 2005-12-15 CN CN2005800437188A patent/CN101095197B/zh not_active Expired - Fee Related
- 2005-12-22 TW TW094146434A patent/TWI308337B/zh not_active IP Right Cessation
-
2007
- 2007-04-13 US US11/735,265 patent/US7397698B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05258583A (ja) * | 1992-03-02 | 1993-10-08 | Nec Corp | 不揮発性記憶装置の制御方法 |
JPH08102198A (ja) * | 1994-09-30 | 1996-04-16 | Nec Corp | 電気的書換え可能な不揮発性半導体記憶装置の初期化方 法 |
JPH09306185A (ja) * | 1996-05-17 | 1997-11-28 | Matsushita Electron Corp | 半導体記憶装置及びその駆動方法 |
JPH11177070A (ja) * | 1997-12-10 | 1999-07-02 | Sony Corp | 不揮発性半導体記憶装置及びその駆動方法 |
JP2000236031A (ja) * | 1999-02-16 | 2000-08-29 | Toshiba Corp | 不揮発性半導体記憶装置 |
WO2004109806A1 (ja) * | 2003-06-04 | 2004-12-16 | Fujitsu Limited | 不揮発性半導体メモリ |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8345484B2 (en) | 2009-08-24 | 2013-01-01 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and system, and method of programming a nonvolatile memory device |
JP2011159364A (ja) * | 2010-02-02 | 2011-08-18 | Toshiba Corp | 不揮発性半導体記憶装置および不揮発性半導体記憶装置の駆動方法 |
KR101261129B1 (ko) | 2010-02-02 | 2013-05-06 | 가부시끼가이샤 도시바 | 불휘발성 반도체 기억 장치 및 그 구동 방법 |
US8559221B2 (en) | 2010-02-02 | 2013-10-15 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for driving same |
WO2012039511A1 (en) * | 2010-09-24 | 2012-03-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US9230665B2 (en) | 2010-09-24 | 2016-01-05 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JP2012160236A (ja) * | 2011-02-01 | 2012-08-23 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2013073639A (ja) * | 2011-09-27 | 2013-04-22 | Lapis Semiconductor Co Ltd | 半導体不揮発性メモリ及びデータ書き込み方法 |
JP2013131275A (ja) * | 2011-12-22 | 2013-07-04 | Toshiba Corp | 不揮発性半導体記憶装置 |
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US20060140011A1 (en) | 2006-06-29 |
US20070195602A1 (en) | 2007-08-23 |
WO2006071541A1 (en) | 2006-07-06 |
CN101095197A (zh) | 2007-12-26 |
US7397698B2 (en) | 2008-07-08 |
US7230851B2 (en) | 2007-06-12 |
TW200638426A (en) | 2006-11-01 |
CN101095197B (zh) | 2010-05-12 |
EP1829046A1 (en) | 2007-09-05 |
KR100868805B1 (ko) | 2008-11-17 |
TWI308337B (en) | 2009-04-01 |
KR20070101255A (ko) | 2007-10-16 |
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