JP2008508719A - 高k誘電材料と一緒に使用するための界面層 - Google Patents

高k誘電材料と一緒に使用するための界面層 Download PDF

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Publication number
JP2008508719A
JP2008508719A JP2007523561A JP2007523561A JP2008508719A JP 2008508719 A JP2008508719 A JP 2008508719A JP 2007523561 A JP2007523561 A JP 2007523561A JP 2007523561 A JP2007523561 A JP 2007523561A JP 2008508719 A JP2008508719 A JP 2008508719A
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layer
germanium
depositing
substrate
silicon
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Japanese (ja)
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JP2008508719A5 (enExample
Inventor
トーマス,ショーン・ジー
マニアー,パプ・ディー
イルデレム,ヴィダ
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NXP USA Inc
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NXP USA Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28255Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
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    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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    • H10D64/60Electrodes characterised by their materials
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    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
JP2007523561A 2004-07-30 2005-06-16 高k誘電材料と一緒に使用するための界面層 Pending JP2008508719A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/903,841 US7320931B2 (en) 2004-07-30 2004-07-30 Interfacial layer for use with high k dielectric materials
PCT/US2005/021498 WO2006023027A1 (en) 2004-07-30 2005-06-16 Interfacial layer for use with high k dielectric materials

Publications (2)

Publication Number Publication Date
JP2008508719A true JP2008508719A (ja) 2008-03-21
JP2008508719A5 JP2008508719A5 (enExample) 2008-08-07

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JP2007523561A Pending JP2008508719A (ja) 2004-07-30 2005-06-16 高k誘電材料と一緒に使用するための界面層

Country Status (6)

Country Link
US (1) US7320931B2 (enExample)
JP (1) JP2008508719A (enExample)
KR (1) KR20070044441A (enExample)
CN (1) CN100481319C (enExample)
TW (1) TW200625657A (enExample)
WO (1) WO2006023027A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7399666B2 (en) * 2005-02-15 2008-07-15 Micron Technology, Inc. Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US8110469B2 (en) * 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US20070161214A1 (en) * 2006-01-06 2007-07-12 International Business Machines Corporation High k gate stack on III-V compound semiconductors
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
US8330381B2 (en) * 2009-05-14 2012-12-11 Ilumisys, Inc. Electronic circuit for DC conversion of fluorescent lighting ballast
US8268683B2 (en) * 2009-06-12 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing interfacial layer thickness for high-K and metal gate stack
EP2270840B1 (en) * 2009-06-29 2020-06-03 IMEC vzw Method for manufacturing an III-V material substrate and the substrate thereof
CN102509734A (zh) * 2011-11-08 2012-06-20 复旦大学 一种利用ald制备锗基mos电容的方法
CN113823555B (zh) * 2021-09-03 2024-06-07 合肥安德科铭半导体科技有限公司 一种在绝缘体上制备锗薄膜的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129751A (ja) * 1995-09-08 1997-05-16 Max Planck Ges Foerderung Wissenschaft Ev トランジスタ用の半導体構造及び回路
JPH11251593A (ja) * 1997-12-24 1999-09-17 Texas Instr Inc <Ti> ゲルマニウム層を使用した大誘電率ゲートの構造と方法
JP2003086588A (ja) * 2001-09-10 2003-03-20 Nippon Telegr & Teleph Corp <Ntt> Mis型半導体装置の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5326721A (en) * 1992-05-01 1994-07-05 Texas Instruments Incorporated Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer
CN1042775C (zh) * 1996-06-21 1999-03-31 河北工业大学 用锗进行硅/硅键合的方法及其制备的硅器件衬底片
US6800881B2 (en) * 1996-12-09 2004-10-05 Ihp Gmbh-Innovations For High Performance Microelectronics/Institut Fur Innovative Mikroelektronik Silicon-germanium hetero bipolar transistor with T-shaped implantation layer between emitter and emitter contact area
US6723621B1 (en) * 1997-06-30 2004-04-20 International Business Machines Corporation Abrupt delta-like doping in Si and SiGe films by UHV-CVD
FR2783254B1 (fr) * 1998-09-10 2000-11-10 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus
US6184072B1 (en) 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US20030111678A1 (en) 2001-12-14 2003-06-19 Luigi Colombo CVD deposition of M-SION gate dielectrics
US6696332B2 (en) 2001-12-26 2004-02-24 Texas Instruments Incorporated Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
US6620713B2 (en) 2002-01-02 2003-09-16 Intel Corporation Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
JP2004006819A (ja) * 2002-04-26 2004-01-08 Nec Electronics Corp 半導体装置の製造方法
US6621114B1 (en) 2002-05-20 2003-09-16 Advanced Micro Devices, Inc. MOS transistors with high-k dielectric gate insulator for reducing remote scattering
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6617639B1 (en) 2002-06-21 2003-09-09 Advanced Micro Devices, Inc. Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129751A (ja) * 1995-09-08 1997-05-16 Max Planck Ges Foerderung Wissenschaft Ev トランジスタ用の半導体構造及び回路
JPH11251593A (ja) * 1997-12-24 1999-09-17 Texas Instr Inc <Ti> ゲルマニウム層を使用した大誘電率ゲートの構造と方法
JP2003086588A (ja) * 2001-09-10 2003-03-20 Nippon Telegr & Teleph Corp <Ntt> Mis型半導体装置の製造方法

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Publication number Publication date
KR20070044441A (ko) 2007-04-27
WO2006023027A1 (en) 2006-03-02
TW200625657A (en) 2006-07-16
CN100481319C (zh) 2009-04-22
US20060022283A1 (en) 2006-02-02
US7320931B2 (en) 2008-01-22
CN1985352A (zh) 2007-06-20

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