CN100481319C - 用于高k介电材料的界面层 - Google Patents

用于高k介电材料的界面层 Download PDF

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CN100481319C
CN100481319C CNB2005800238837A CN200580023883A CN100481319C CN 100481319 C CN100481319 C CN 100481319C CN B2005800238837 A CNB2005800238837 A CN B2005800238837A CN 200580023883 A CN200580023883 A CN 200580023883A CN 100481319 C CN100481319 C CN 100481319C
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germanium
exposed surface
germanium layer
silicon
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肖恩·G·托马斯
怕普·D·马尼尔
维达·依尔德瑞姆
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NXP USA Inc
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Abstract

提供一种方法和装置，用于在硅衬底(11)上沉积纯锗层(12)。该锗层非常薄，在约14的量级上，并且小于硅上纯锗的临界厚度。该锗层(12)用作硅衬底(11)和高k栅极层(13)之间的中间层，其沉积于锗层(12)之上。锗层(12)有助于避免在施加高k材料期间氧化物界面层的形成。在半导体结构中使用锗中间层导致高k栅极功能性，而不会存在：由于氧化物杂质导致的串联电容的缺点。该锗层(12)还提高了迁移率。

Description

用于高K介电材料的界面层
技术领域
本发明一般涉及一种半导体器件以及其制造方法，且更具体地涉及到使用与高k介电材料和硅衬底一起使用的界面锗层。
背景技术
场效应晶体管(FET)已经在电子工业中发现广泛应用。一些具体处理应用包括开关、放大、滤波和其它任务。金属氧化物场效应晶体管(MOSFET)是现在使用的较通用的FET器件类型中的一种。其已经发现例如在数字处理应用中的重要应用。MOSFET结构典型地包括金属或者多晶硅栅极触点，对栅极触点加电以在半导体沟道中产生电场，其允许电流在源和漏极区之间传导。
根据摩尔定律，设计者继续尝试缩小晶体管的尺寸。随着晶体管变得越来越小，栅极电介质层也已经越来越薄。栅极电介质层厚度的持续降低导致了技术问题。穿过栅极二氧化硅介电层的泄漏随着其厚度的降低而按指数规律增加。今后提出的栅极尺寸将需要介电层如此薄以至偏离纯“开”态和“关”态。代替地，泄漏可导致低功率，或者“漏泄的”关态。为了后一代晶体管的成功必须解决该挑战。
提出的一个替代方案使用高k材料代替二氧化硅作为栅极电介质层。高k指的是高介电常数，这是可以保持多少电荷的量度。不同材料具有不同的保持电荷的能力。高k材料包括氧的化合物如二氧化铪(HfO2)、二氧化锆(ZrO2)和二氧化钛(TiO2)，且具有高于二氧化硅的值3.9的介电常数。
介电常数还影响晶体管性能。随着k值增加，晶体管电容也增加了。该增加的电容允许晶体管在“开”态和“关”态之间正确地转换。而且，较高的k值对应于高质量的转换，从而在“关”态下存在非常小的电流泄漏和在“开”态期间存在高电流。此外，介电叠层中的高k材料能导致最终晶体管中改善的电荷迁移率。良好的电荷迁移率的高k材料特性能够提高晶体管的性能、可靠性和使用寿命。由此，高k材料很希望用作可能用在介电叠层中的材料。
然而，近几十年，电子工业主要使用二氧化硅作为介电层材料。现在，实验性地使用高k材料介电层显示出其它的制造和处理挑战，当使用较厚二氧化硅层时该挑战并不明显。需要克服这些技术挑战，以进一步开发高k材料的应用。当将高k材料用在介电层中的一个特定问题是由于在硅层表面处形成氧化物而导致的差的介电特性。
所提出的用在高k介电层中的很多种材料是包括氧的化合物。而且，在硅衬底上沉积这些材料包括含有氧化步骤的处理步骤。一种元素的化学气相沉积(CVD)或者溅射之后进行的材料氧化是用于形成高k介电层的示意工艺类型。由此，无论是在沉积工艺中作为环境气体存在的还是提供到氧化化合物自身中的氧都存在于接近硅衬底的附近。这种类型制造的结果是出现界面层，该层在硅衬底和高k介电层之间。界面层包括氧化物材料，如二氧化硅，其是与衬底的硅反应的结果。且这些氧化物材料会危害通过高k介电材料另外获得的性能。
薄二氧化硅层作用上是低k界面层。这种类型的低k界面层在电子方面用作与高k介电层串联的电容器。二氧化硅界面层的作用是降低栅极介电叠层的整个电容，由此消除了使用高k材料的优点。此外，该界面层导致沟道区(正在栅极电介质层下方)中迁移率降低，并由此降低与其相关的器件性能。
因此，希望得到新的材料和将这些材料用在高k介电层中的方法。所需工艺和材料应当减少或者消除在之前与栅极电介质层中高k材料一起使用中所注意到的界面氧化层的影响。此外，希望开发出这些材料和方法，以使其适合于与FET制造中使用的当前处理技术一起使用。还希望使用高k介电材料以便改善半导体中的电荷迁移率，并由此改善半导体使用寿命。本发明满足了这些需要中的一个或多个。而且，结合附图和本发明的背景，根据本发明随后的详细描述和附属的权利要求，本发明其它希望的特征和性能变得明显。
发明内容
根据本发明的一个方面，提供一种半导体结构，包括：衬底；锗层，其沉积在衬底表面上，其中，锗层厚度小于约
Figure C200580023883D00061
和沉积在锗层上的高k材料的单个介电层或者多个介电层的叠层。
根据本发明的另一方面，提供一种形成半导体结构的方法，包括步骤：提供具有暴露表面的衬底；在硅层的暴露表面上形成锗层，以使锗层厚度小于约
Figure C200580023883D00062
且其中沉积的锗层具有暴露的表面；和在锗层的暴露的表面上形成高k材料的单个介电层或者多个介电层的叠层。
根据本发明的再一方面，提供一种形成半导体结构的方法，包括步骤：提供具有暴露表面的高纯单晶衬底层；清洗硅层的暴露的表面以降低氧化物的存在；在衬底层的暴露的表面上沉积高纯锗层，其中锗层与硅层外延匹配，且使得锗层小于临界厚度，并且其中沉积的锗层具有暴露的表面；清洗衬底层的暴露的表面以降低氧化物的存在；以及在锗层的暴露的表面上沉积高k材料介电层。
附图说明
以下将结合附图描述本发明，无论何时相似的参考数字都表示相似的元件，且其中：
图1是使用根据本发明实施例锗界面层的半导体结构的透视图；
图2是用根据本发明实施例的处理步骤形成的晶体管结构的透视图；
图3是根据本发明实施例锗晶体和硅晶体的晶格结构的透视图；
图4是以2维结构在硅层上生长的锗层的透视图；
图5是以3维结构在硅层上生长的锗材料的透视图。
具体实施方式
实际上对本发明的下面详细描述仅仅是示范性的，且不想限制本发明或者本发明的应用或者使用。而且，不想限于在本发明前述背景技术或者对本发明的以下详细描述中给出的任何理论。
现在，公开了在硅衬底上生长纯锗层。该锗层非常薄，在约
Figure C200580023883D00071
的量级上，且小于硅上纯外延锗的临界厚度。该锗层用作硅衬底和高k栅极层之间的中间层。该锗层有助于避免在应用高k材料期间形成氧化物界面层。应用锗中间层导致高k栅极功能性，而不会导致由于氧化物杂质而产生的串联电容的缺点。
现在参考图1，示出了根据本发明实施例使用锗层的半导体结构的示意图。本领域技术人员将理解，对图1中示出的半导体结构进行处理，以便将晶体管结构从图1的多层结构转换为图2中示出的完成的晶体管。如图1中所示，该结构包括硅基底层11、薄锗层12和高k材料的介电层13。硅层11是如硅基半导体制造中所使用的硅衬底。替代的硅层11可包括绝缘体上硅材料(SOI)。
在替代实施例中，层11可包括除了硅之外的材料。可选材料包括砷化镓(GaAs)、磷化铟(InP)、GaAs的任意合金化合物以及InP的任意合金化合物。
现在参考图2，示出了完成的晶体管的典型实例。该晶体管可以由图1的开始结构制造。除了硅基底层11、锗层12和介电层13之外，完成的晶体管还包括源极区14和漏极区15。此外，已经定形了介电叠层的物理几何形状，以将介电层13转换成栅极。本领域技术人员将理解，这是制造工艺的一部分，以将半导体叠层转换成完成的晶体管。
形成图1中示出的半导体结构的方法始于制备硅衬底11。这能够通过在半导体技术中使用的任意公知工序来实现。例如，衬底可以是体硅衬底。替代地，半导体衬底可以是绝缘体上类型的硅衬底。衬底还可包括掺杂剂如p掺杂。形成衬底11将提供(render)衬底的暴露表面，在其上将沉积进一步的材料层，在这种情况下沉积锗层12。在优选实施例中，暴露的硅表面是基本上没有表面氧化物的单晶材料。由此，还优选硅层11包括单晶硅材料。
除了产生硅衬底11的步骤之外，衬底11另外受到可选的处理，以去除或减少暴露表面上的氧化物。清洗工序包括用氢氟酸溶液清洗暴露的表面，以及在半导体工业中使用的其它清洗工序。该清洗工序可遵循本领域中公知的外部或原位(ex-situ or in-situ)清洗方法。另外优选硅材料尤其在暴露表面处基本不受污染。如本领域中所公知的，对硅衬底11的处理可发生在真空中或者在惰性气氛下，以最小化氧的存在。
在接下来的步骤中，将锗层12沉积在硅层的暴露表面上。在完成该步骤中，锗层12覆盖事先暴露的硅表面或者部分暴露表面。一旦完成锗层12，其现在具有暴露表面。可将随后的材料如高k材料沉积在该表面上。
在一个实施例中，锗层12优选为高纯锗。该实施例中，可避免锗中的杂质或其他材料。这优选锗层厚度在临界厚度以下。替代的锗层12包括少量的碳。
在硅上沉积锗层的方法包括分子束外延(MBE)和化学气相沉积(CVD)。MBE是允许精密控制原子级材料生长的方法。MBE还允许优良控制、可重复且完全地沉积薄外延层。由此，MBE非常适合于沉积薄锗层。分子束外延在超高真空环境中采用固态源蒸镀；材料通常通过供给系统如气动挡板(pneumatic shutter)单独受控制。该工艺提供灵活性并允许以高度可重复性在计算机控制下制造复杂合金和超晶格结构。
在MBE沉积方法的一个实施例中，首先将硅晶片设置在MBE室中。将锗源装载于一个或多个泄流室(effusion cell)中。将每个泄流室加热到所需等级，以促进锗的质量传递。优选排空MBE室以提供高真空度。将硅晶片加热到所需温度以促进晶片上锗的外延生长。打开MBE装置中的挡板，以将锗暴露到MBE室达所需时间长度。对MBE沉积普遍的其它控制如硅晶片旋转也包括在系统中。选择控制参数如时间、温度和能量转移，以促进硅衬底上锗的外延、2维生长。
其它可选沉积工序也可用于形成锗层。这些方法包括金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)、原子气相沉积(AVD)、物理气相沉积(PVD)、化学溶液沉积(CSD)、脉冲激光沉积(PLD)等。
现在参考图3，示出了与硅晶体相匹配的锗晶格的图。该晶体的硅部分示出为层30，且锗部分是层31。锗和硅的晶格结构通过其自身失配，这在于，在纯锗晶体中锗原子之间间距大于在纯硅晶体中硅原子之间的间距。然而，在一定厚度以下，锗晶体层能够外延生长到硅晶体层上。在低于临界厚度的厚度时，锗晶格结构中的锗原子能够适合于匹配硅的晶格结构。锗晶格延伸或者挤压以通过在垂直方向上膨胀锗晶格来在水平面上与硅匹配。然而在厚度超出临界厚度时，锗晶体不能受到拉伸应变以适应硅晶体；锗晶体将弛豫，并由此在某一点上断裂。该断裂点称作临界厚度。对于与硅晶体相匹配的锗薄层，该临界厚度接近
Figure C200580023883D00091
该临界厚度对应于在晶格中锗原子的约3至4个原子层。由此，优选锗晶格具有锗原子的3个或更少的原子层。
优选在衬底上生长的锗层假同晶地(pseudomorphically)形成于衬底上，这意味着锗是与锗临界厚度和衬底材料相符的外延晶格。而且，优选的假同晶生长形成了锗层，而没有位错。可选地，优选衬底层与锗具有小于4.2％的晶格失配。除了硅、砷化镓、磷化铟和其合金之外的优选衬底层具有比硅本身与锗更加接近匹配的晶格间距。由此，在这些材料上生长锗层在锗层中产生较小的应力。砷化镓、磷化铟和其合金相对于锗具有小于4.2％的晶格失配。
可在硅上生长锗层至大于临界厚度的厚度。这通过在锗中包括少量碳来实现。在锗晶格中的碳原子允许锗晶体弛豫而不会破裂。由此，当锗晶体与硅晶格相匹配且将其生长到超出临界厚度时，在锗晶体中的应力在碳位置处得到解决。通常，在锗中1％浓度的碳原子将使锗晶体弛豫大约10％。在一个替代实施例中，锗层包括高达5重量％的碳。这在希望锗层比临界厚度大时是优选的。
优选在Stranski-Krastanov生长模式下生长锗界面层。在硅上生长的锗能够以2维模式(Stranski-Krastanov)或者3维模式(Volmer-Weber)生长。现在参考附图，图4A示出了在硅衬底11上锗层12的2维生长，图4B示出了在硅衬底11上锗“岛”16的3维生长。2维生长特征在于，锗层的生长；这些层可以是原子层。在2维生长模式中，锗的第一原子层沉积在硅表面上。这之后是在第一层上沉积锗的第二原子层。相反地，3维生长特征在于，成簇或“岛”地沉积锗材料，其中每个锗岛本身都由很多锗原子层构成。而且，在3维生长模式下，锗岛不相互接触，以使得硅表面之间的部分仍然暴露出。由于2维模式下生长的纯锗层超过了临界厚度，因此在锗晶格弛豫时，锗生长会转换到3维生长模式。由此，对于硅上的纯锗，锗层应保持为临界厚度或者低于临界厚度，接近
Figure C200580023883D00101
优选锗层生长不从2维生长转换为3维生长。
部分地由于在硅上沉积锗不会产生否则将形成二氧化硅界面层的明显水平的氧化物，因此将锗选作界面层的优选材料。锗不容易形成化学稳定的氧化物结构。由此，当在缺氧气氛中将纯锗沉积到硅上时，可使氧化物最少。最小化与硅反应的氧。由此，避免了现有技术方法中的困难。本领域技术人员还应进一步理解，之后应实施良好的制造方法，以便最小化氧化物的存在。这例如包括，在真空或者惰性气氛中的操作，以避免氧的存在。使用高纯材料也将最小化氧化物的存在。
对已经被沉积的锗层12进一步处理，以降低任何氧的存在。该处理包括清洗步骤，如用氢氟酸溶液或者其他清洗剂的处理。在这一点上，锗层的暴露表面容易沉积介电层中的高k材料。
将该介电层沉积到锗层的暴露表面上。在优选实施例中，介电层厚度小于
Figure C200580023883D00102
可应用在锗上沉积高k材料的公知方法。
如在此所使用的，术语“高k”或者“高k介电材料”意思是具有大约10或更大的k值的介电材料。这种高k介电材料例如包括氧化铪、氧化锆、氧化镧、氧化钛、氧化铝等。总之，高k介电材料包括那些二元、三元或更高元氧化物以及具有约20或更大的k值的铁电材料。而且，高k介电材料包括复合材料如硅酸铪、其他硅酸盐、氧氮硅铪、氧氮化锗以及其他氧氮化物。
当材料涉及到具体的化学名称或者化学式时，该材料可包括由化学名称表示的化学计量精确公式的非化学计量变形。由此，例如，氧化铪可包括化学式HfO2的化学计量精确的合成物以及HfxOy二者，其中x和y的任一个可分别从1和2改变一定量。
虽然本发明前面的详细描述已经说明了至少一个示范性实施例，但是应当理解，还存在很多变形。还应当理解，一个或多个示范性实施例仅仅是实例，且不想其以任何方式限制本发明的范围、可应用性或结构。而是，前面的详细描述将为本领域技术人员提供便利的路标，以实施本发明的示范性实施例，可以理解，在示范性实施例中描述的功能和设置方面均可作出各种改变，而不背离如由附属的权利要求中所列出的本发明的范围。

Claims (6)

1.一种形成半导体结构的方法，包括步骤：
提供具有暴露表面的硅衬底；
抑制在硅衬底的暴露表面上形成一个或多个氧化物，其中抑制包括以下步骤：
清洗硅衬底的暴露表面以减少氧化物的存在；
直接在清洗后的硅衬底的暴露表面上沉积纯的锗层，使得锗层厚度小于14
Figure C200580023883C0002104611QIETU
并且与所述硅衬底外延匹配，其中沉积的纯的锗层具有暴露表面；和
清洗纯的锗层的暴露表面以减少氧化物的存在；以及
直接在清洗后的纯的锗层的暴露表面上形成高k材料的介电层。
2.如权利要求1的方法，其中提供衬底层的步骤还包括提供具有单晶硅的暴露表面的硅层。
3.如权利要求2的方法，其中沉积锗层的步骤还包括以2维生长模式生长锗层。
4.一种形成半导体结构的方法，包括步骤：
提供具有暴露表面的单晶硅衬底层；
抑制在衬底的暴露表面上形成一个或多个氧化物，其中抑制包括以下步骤：
清洗衬底层的暴露表面以减少氧化物的存在；
在清洗后的衬底层的暴露表面上沉积锗层，其中锗层与衬底层外延匹配并且包括高达5重量％的碳，并且使得锗层小于临界厚度，并且其中沉积的锗层具有暴露表面；和
清洗锗层的暴露表面以减少氧化物的存在；以及
在清洗后的锗层的暴露表面上沉积高k材料的介电层。
5.如权利要求4的方法，其中沉积锗层的步骤还包括沉积锗层，以使锗层的厚度小于
Figure C200580023883C00021
6.如权利要求5的方法，其中沉积介电层的步骤还包括沉积厚度小于
Figure C200580023883C00031
的介电层。
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