JP2008504704A5 - - Google Patents

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Publication number
JP2008504704A5
JP2008504704A5 JP2007518571A JP2007518571A JP2008504704A5 JP 2008504704 A5 JP2008504704 A5 JP 2008504704A5 JP 2007518571 A JP2007518571 A JP 2007518571A JP 2007518571 A JP2007518571 A JP 2007518571A JP 2008504704 A5 JP2008504704 A5 JP 2008504704A5
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JP
Japan
Prior art keywords
semiconductor layer
semiconductor
relaxed
layer
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007518571A
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English (en)
Japanese (ja)
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JP2008504704A (ja
JP5089383B2 (ja
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Publication date
Priority claimed from US10/883,887 external-priority patent/US7172930B2/en
Application filed filed Critical
Publication of JP2008504704A publication Critical patent/JP2008504704A/ja
Publication of JP2008504704A5 publication Critical patent/JP2008504704A5/ja
Application granted granted Critical
Publication of JP5089383B2 publication Critical patent/JP5089383B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007518571A 2004-07-02 2005-05-27 埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ Expired - Fee Related JP5089383B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/883,887 2004-07-02
US10/883,887 US7172930B2 (en) 2004-07-02 2004-07-02 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
PCT/EP2005/052424 WO2006003061A1 (en) 2004-07-02 2005-05-27 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER

Publications (3)

Publication Number Publication Date
JP2008504704A JP2008504704A (ja) 2008-02-14
JP2008504704A5 true JP2008504704A5 (enExample) 2008-05-29
JP5089383B2 JP5089383B2 (ja) 2012-12-05

Family

ID=34969794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007518571A Expired - Fee Related JP5089383B2 (ja) 2004-07-02 2005-05-27 埋め込みｐ＋シリコン・ゲルマニウム層の陽極酸化による歪みシリコン・オン・インシュレータ

Country Status (7)

Country Link
US (3) US7172930B2 (enExample)
EP (1) EP1779423A1 (enExample)
JP (1) JP5089383B2 (enExample)
KR (1) KR100961815B1 (enExample)
CN (1) CN101120442A (enExample)
TW (1) TWI359477B (enExample)
WO (1) WO2006003061A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7172930B2 (en) * 2004-07-02 2007-02-06 International Business Machines Corporation Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
US7235812B2 (en) * 2004-09-13 2007-06-26 International Business Machines Corporation Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
RU2331949C1 (ru) * 2006-12-21 2008-08-20 Институт физики полупроводников Сибирского отделения Российской академии наук Способ получения структуры "кремний-на-изоляторе"
US7833884B2 (en) * 2007-11-02 2010-11-16 International Business Machines Corporation Strained semiconductor-on-insulator by Si:C combined with porous process
US7772096B2 (en) * 2008-07-10 2010-08-10 International Machines Corporation Formation of SOI by oxidation of silicon with engineered porosity gradient
JP5444899B2 (ja) * 2008-09-10 2014-03-19 ソニー株式会社 固体撮像装置の製造方法、および固体撮像装置の製造基板
US20100221867A1 (en) * 2009-05-06 2010-09-02 International Business Machines Corporation Low cost soi substrates for monolithic solar cells
US20120091100A1 (en) * 2010-10-14 2012-04-19 S.O.I.Tec Silicon On Insulator Technologies Etchant for controlled etching of ge and ge-rich silicon germanium alloys
EP2498280B1 (en) 2011-03-11 2020-04-29 Soitec DRAM with trench capacitors and logic back-biased transistors integrated on an SOI substrate comprising an intrinsic semiconductor layer and manufacturing method thereof
US8518807B1 (en) * 2012-06-22 2013-08-27 International Business Machines Corporation Radiation hardened SOI structure and method of making same
US8975125B2 (en) 2013-03-14 2015-03-10 International Business Machines Corporation Formation of bulk SiGe fin with dielectric isolation by anodization
US9590077B2 (en) 2015-05-14 2017-03-07 International Business Machines Corporation Local SOI fins with multiple heights
US9385023B1 (en) 2015-05-14 2016-07-05 Globalfoundries Inc. Method and structure to make fins with different fin heights and no topography
US9627536B2 (en) 2015-06-25 2017-04-18 International Busines Machines Corporation Field effect transistors with strained channel features
US9559120B2 (en) 2015-07-02 2017-01-31 International Business Machines Corporation Porous silicon relaxation medium for dislocation free CMOS devices

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104090A (en) * 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
JPS5831730B2 (ja) * 1979-10-15 1983-07-08 松下電器産業株式会社 半導体装置の製造方法
US6469357B1 (en) * 1994-03-23 2002-10-22 Agere Systems Guardian Corp. Article comprising an oxide layer on a GaAs or GaN-based semiconductor body
JPH0864674A (ja) * 1994-08-04 1996-03-08 Lg Semicon Co Ltd 半導体素子の絶縁方法
US6043166A (en) * 1996-12-03 2000-03-28 International Business Machines Corporation Silicon-on-insulator substrates using low dose implantation
US6090689A (en) * 1998-03-04 2000-07-18 International Business Machines Corporation Method of forming buried oxide layers in silicon
US5930643A (en) * 1997-12-22 1999-07-27 International Business Machines Corporation Defect induced buried oxide (DIBOX) for throughput SOI
US6486037B2 (en) * 1997-12-22 2002-11-26 International Business Machines Corporation Control of buried oxide quality in low dose SIMOX
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
US6607948B1 (en) * 1998-12-24 2003-08-19 Kabushiki Kaisha Toshiba Method of manufacturing a substrate using an SiGe layer
US5950094A (en) 1999-02-18 1999-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating fully dielectric isolated silicon (FDIS)
TW591132B (en) * 1999-06-17 2004-06-11 Taiwan Semiconductor Mfg Method of growing SiGe epitaxy
JP4212228B2 (ja) * 1999-09-09 2009-01-21 株式会社東芝 半導体装置の製造方法
JP2003158075A (ja) * 2001-08-23 2003-05-30 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ
US7101772B2 (en) * 2000-12-30 2006-09-05 Texas Instruments Incorporated Means for forming SOI
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US6602757B2 (en) * 2001-05-21 2003-08-05 International Business Machines Corporation Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI
US6541356B2 (en) * 2001-05-21 2003-04-01 International Business Machines Corporation Ultimate SIMOX
US6846727B2 (en) * 2001-05-21 2005-01-25 International Business Machines Corporation Patterned SOI by oxygen implantation and annealing
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
US20020190318A1 (en) * 2001-06-19 2002-12-19 International Business Machines Corporation Divot reduction in SIMOX layers
US6717213B2 (en) 2001-06-29 2004-04-06 Intel Corporation Creation of high mobility channels in thin-body SOI devices
US7138649B2 (en) * 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
KR100442105B1 (ko) * 2001-12-03 2004-07-27 삼성전자주식회사 소이형 기판 형성 방법
US6495429B1 (en) * 2002-01-23 2002-12-17 International Business Machines Corporation Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing
KR100476901B1 (ko) * 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
JP3873012B2 (ja) * 2002-07-29 2007-01-24 株式会社東芝 半導体装置の製造方法
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6812116B2 (en) * 2002-12-13 2004-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
JP4344517B2 (ja) * 2002-12-27 2009-10-14 富士通株式会社 半導体基板及びその製造方法
WO2004073043A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Semiconductor-on-insulator article and method of making same
WO2004073044A2 (en) * 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7071052B2 (en) * 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
US7125458B2 (en) * 2003-09-12 2006-10-24 International Business Machines Corporation Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US7023055B2 (en) * 2003-10-29 2006-04-04 International Business Machines Corporation CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US7183593B2 (en) * 2003-12-05 2007-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructure resistor and method of forming the same
US7202133B2 (en) * 2004-01-21 2007-04-10 Chartered Semiconductor Manufacturing, Ltd. Structure and method to form source and drain regions over doped depletion regions
US7923782B2 (en) * 2004-02-27 2011-04-12 International Business Machines Corporation Hybrid SOI/bulk semiconductor transistors
JP4177775B2 (ja) * 2004-03-16 2008-11-05 株式会社東芝 半導体基板及びその製造方法並びに半導体装置
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US7172930B2 (en) * 2004-07-02 2007-02-06 International Business Machines Corporation Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
US7585792B2 (en) * 2005-02-09 2009-09-08 S.O.I.Tec Silicon On Insulator Technologies Relaxation of a strained layer using a molten layer

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